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ATSAM4S-XPLD
433
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
27.
Peripheral DMA Controller (PDC)
27.1
Description
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip
memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge.
memories. The link between the PDC and a serial peripheral is operated by the AHB to APB bridge.
The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface
of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit
counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bi-directional
channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used
by current transmit, next transmit, current receive and next receive.
of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit
counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bi-directional
channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used
by current transmit, next transmit, current receive and next receive.
Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces
the number of clock cycles required for a data transfer, which improves microcontroller performance.
the number of clock cycles required for a data transfer, which improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When
the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
27.2
Embedded Characteristics
Handles data transfer between peripherals and memories
Low bus arbitration overhead
One Master Clock cycle needed for a transfer from memory to peripheral
Two Master Clock cycles needed for a transfer from peripheral to memory
Next Pointer management for reducing interrupt latency requirement
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to
High priorities):
High priorities):
Table 27-1. Peripheral DMA Controller
Instance Name
Channel T/R
PWM
Transmit
TWI1
Transmit
TWI0
Transmit
UART1
Transmit
UART0
Transmit
USART1
Transmit
USART0
Transmit
DACC
Transmit
SPI
Transmit
SSC
Transmit
HSMCI
Transmit
PIOA
Receive
TWI1
Receive
TWI0
Receive
UART1
Receive
UART0
Receive
USART1
Receive