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ATSAM4S-XPLD
435
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
27.4
Functional Description
27.4.1 Configuration
The PDC channel user interface enables the user to configure and control data transfers for each channel. The user
interface of each PDC channel is integrated into the associated peripheral user interface.
interface of each PDC channel is integrated into the associated peripheral user interface.
The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR,
TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each
type are programmed differently: the transmit and receive parts of a full duplex peripheral can be programmed at the
same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time.
TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each
type are programmed differently: the transmit and receive parts of a full duplex peripheral can be programmed at the
same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time.
32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write
(receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to read the number
of transfers left for each channel.
(receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to read the number
of transfers left for each channel.
The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status
for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by
setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control Register.
for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by
setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral’s Transfer Control Register.
At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the
peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to
peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to
peripheral user interface.
27.4.2 Memory Pointers
Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have
32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory.
32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory.
Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory
pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data
depending on the operating mode of the peripheral.
pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data
depending on the operating mode of the peripheral.
Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4
bytes.
bytes.
If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new
address.
address.