Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 449

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The Clock Generator User Interface is embedded within the Power Management Controller and is 
described in 

Clock Generator registers are named CKGR_.

The Clock Generator is made up of:



A Low Power 32768 Hz Slow Clock Oscillator with bypass mode.



A Low Power RC Oscillator



A 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator, which can be bypassed.



A factory programmed Fast RC Oscillator. Three output frequencies can be selected: 
12/8/4 MHz. By default 4 MHz is selected.



Two 80 to 240 MHz programmable PLL (input from 3 to 32 MHz), capable of providing the 
clock MCK to the processor and to the peripherals.



Write Protected Registers

It provides the following clocks:



SLCK, the Slow Clock, which is the only permanent clock within the system.



MAINCK is the output of the Main Clock Oscillator selection: either the Crystal or Ceramic 
Resonator-based Oscillator or 12/8/4 MHz Fast RC Oscillator.



PLLACK is the output of the Divider and 80 to 240 MHz programmable PLL (PLLA).



PLLBCK is the output of the Divider and 80 to 240 MHz programmable PLL (PLLB).