Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 455

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

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If MOSCSELS=0, the crystal oscillator can be disabled (MOSCXTEN=0 in the 
CKGR_MOR register).

The device features a Main Clock frequency counter that provides the frequency of the Main Clock. 

The Main Clock frequency counter is reset and starts incrementing at the Main Clock speed after the 
next rising edge of the Slow Clock in the following cases:

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When the 12/8/4 MHz Fast RC Oscillator clock is selected as the source of Main Clock and 
when this oscillator becomes stable (i.e., when the MOSCRCS bit is set)

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When the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is selected as the 
source of Main Clock and when this oscillator becomes stable (i.e., when the MOSCXTS bit is 
set)

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When the Main Clock Oscillator selection is modified

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When the RCMEAS bit of CKGR_MFCR is written to 1.

Then, at the 16th falling edge of Slow Clock, the MAINFRDY bit in the Clock Generator Main Clock 
Frequency Register (CKGR_MCFR) is set and the counter stops counting. Its value can be read in 
the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of 
Slow Clock, so that the frequency of the 12/8/4 MHz Fast RC Oscillator or 3 to 20 MHz Crystal or 
Ceramic Resonator-based Oscillator can be determined.

The device features two Divider/two PLL Blocks that permit a wide range of frequencies to be 
selected on either the master clock, the processor clock or the programmable clock outputs. 
Additionally, they provide a 48 MHz signal to the embedded USB device port regardless of the 
frequency of the main clock.