Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 456

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the 
output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, 
each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.

The PLLs (PLLA, PLLB) allow multiplication of the divider’s outputs. The PLL clock signal has a 
frequency that depends on the respective source signal frequency and on the parameters DIV (DIVA, 
DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is (MUL + 1)/DIV. 
When MUL is written to 0 or DIV=0, the PLL is disabled and its power consumption is saved. Re-
enabling the PLL can be performed by writing a value higher than 0 in the MUL field and DIV higher 
than 0.

Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK (LOCKA, LOCKB) bit 
in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT, 
PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR, CKGR_PLLBR) are loaded in the PLL counter. The 
PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK 
bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of 
Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field.

The PLL clock can be divided by 2 by writing the PLLDIV2 (PLLADIV2, PLLBDIV2) bit in PMC Master 
Clock Register (PMC_MCKR).

It is forbidden to change 12/8/4 MHz Fast RC Oscillator, or main selection in CKGR_MOR register 
while Master Clock source is PLL and PLL reference clock is the Fast RC Oscillator.

The user must: 

Divider B

DIVB

PLL B

MULB

DIVA

PLL A

Counter

PLLBCOUNT

LOCKB

PLL A

Counter

PLLACOUNT

LOCKA

MULA

OUTB

OUTA

SLCK

PLLACK

PLLBCK

Divider A

PLL B

MAINCK

PLLADIV2

PLLBDIV2