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ATSAM4S-XPLD
459
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.3 Block Diagram
Figure 28-5. General Clock Block Diagram
28.2.4 Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the
clock provided to all the peripherals. The Master Clock is selected from one of the clocks provided by
the Clock Generator.
clock provided to all the peripherals. The Master Clock is selected from one of the clocks provided by
the Clock Generator.
Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock
saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector
and a prescaler.
saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector
and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR
(Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock
between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs the prescaler.
(Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock
between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared
in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a
lower one to inform the software when the change is actually done.
in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can
trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a
lower one to inform the software when the change is actually done.
USB Clock
UDPCK
Management
Controller
Main Clock
MAINCK
MAINCK
PLLA Clock
PLLACK
PLLACK
Control
Status
3-20 MHz
Crystal
or
Ceramic
Resonator
Oscillator
MOSCSEL
PLLA and
Divider /2
Divider /2
XIN
XOUT
XIN32
XOUT32
SLCK
(Supply Controller)
Embedded
32 kHz RC
32 kHz RC
Oscillator
32768 Hz
Crystal
Oscillator
PLLB Clock
PLLBCK
PLLBCK
0
1
0
1
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLACK
Prescaler
/1, /2, /3, /4, /8,
/16, /32, /64
HCLK
Processor
Clock
Controller
Sleep Mode
Master Clock Controller
(PMC_MCKR)
ON/OFF
Prescaler
/1, /2, /4, /8,
/16, /32, /64
/16, /32, /64
pck[..]
PLLBCK
ON/OFF
FCLK
SysTick
Divider
/8
SLCK
MAINCK
PLLACK
PLLBCK
Processor clock
Free Running Clock
Master Clock
PLLB and
Divider /2
Divider
/1, /2, /3,... /16
USB Clock Controller (PMC_USB)
PLLBCK
Embedded
4/8/12 MHz
Fast
RC Oscillator
Programmable Clock Controller
(PMC_PCKx)
PRES
USBDIV
PLLADIV2
PLLBDIV2
PRES
USBS
PLLACK
CSS
ON/OFF
CSS
MCK
Clock Generator
XTALSEL
Power
Slow Clock
Peripherals
Clock Controller
(PMC_PCERx)
Clock Controller
(PMC_PCERx)