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ATSAM4S-XPLD
460
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 28-6. Master Clock Controller
28.2.5 Processor Clock Controller
The PMC features a Processor Clock Controller (HCLK) that implements the Processor Sleep Mode.
The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE
(WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Start-up Mode
Register (PMC_FSMR).
The Processor Clock can be disabled by executing the WFI (WaitForInterrupt) or the WFE
(WaitForEvent) processor instruction while the LPM bit is at 0 in the PMC Fast Start-up Mode
Register (PMC_FSMR).
The Processor Clock HCLK is enabled after a reset and is automatically re-enabled by any enabled
interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock, which is
automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product.
interrupt. The Processor Sleep Mode is achieved by disabling the Processor Clock, which is
automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product.
When Processor Sleep Mode is entered, the current instruction is finished before the clock
is stopped, but this does not prevent data transfers from other masters of the system bus.
is stopped, but this does not prevent data transfers from other masters of the system bus.
28.2.6 SysTick Clock
The SysTick calibration value is fixed to 12500 which allows the generation of a time base of 1 ms
with SysTick clock to the maximum frequency on MCK divided by 8.
with SysTick clock to the maximum frequency on MCK divided by 8.
28.2.7 USB Clock Controller
The user can select the PLLA or the PLLB output as the USB Source Clock by writing the USBS bit in
PMC_USB. If using the USB, the user must program the PLL to generate an appropriate frequency
depending on the USBDIV bit in PMC_USB.
PMC_USB. If using the USB, the user must program the PLL to generate an appropriate frequency
depending on the USBDIV bit in PMC_USB.
When the PLL output is stable, i.e., the LOCK bit is set:
The USB device clock can be enabled by setting the UDP bit in PMC_SCER. To save power
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit
in PMC_SCSR gives the activity of this clock. The USB device port requires both the 48 MHz
signal and the Master Clock. The Master Clock may be controlled by means of the Master
Clock Controller.
on this peripheral when it is not used, the user can set the UDP bit in PMC_SCDR. The UDP bit
in PMC_SCSR gives the activity of this clock. The USB device port requires both the 48 MHz
signal and the Master Clock. The Master Clock may be controlled by means of the Master
Clock Controller.
Figure 28-7. USB Clock Controller
SLCK
Master Clock
Prescaler
To the MCK Divider
PRES
CSS
MAINCK
PLLACK
PLLBCK
To the Processor
Clock Controller (PCK)
Clock Controller (PCK)
PMC_MCKR
PMC_MCKR
USB
Source
Clock
UDP Clock (UDPCK)
UDP
USBDIV
Divider
/1,/2,/3,.../16