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ATSAM4S-XPLD
463
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
The user interface does not provide any status for Fast Start-up, but the user can easily recover this
information by reading the PIO Controller and the status registers of the RTC, RTT and USB
Controller.
information by reading the PIO Controller and the status registers of the RTC, RTT and USB
Controller.
28.2.12 Main Crystal Clock Failure Detector
The clock failure detector monitors the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator to
identify an eventual defect of this oscillator (for example, if the crystal is unconnected).
identify an eventual defect of this oscillator (for example, if the crystal is unconnected).
The clock failure detector can be enabled or disabled by means of the CFDEN bit in the PMC Clock
Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled. However, if
the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the clock failure detector
is disabled too.
Generator Main Oscillator Register (CKGR_MOR). After reset, the detector is disabled. However, if
the 3 to 20 MHz Crystal or Ceramic Resonator-based Oscillator is disabled, the clock failure detector
is disabled too.
The slow RC oscillator must be enabled.The clock failure detection must be enabled only when
system clock MCK selects the fast RC Oscillator. Then the status register must be read 2 slow clock
cycles after enabling.
system clock MCK selects the fast RC Oscillator. Then the status register must be read 2 slow clock
cycles after enabling.
A failure is detected by means of a counter incrementing on the 3 to 20 MHz Crystal oscillator or
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal is
low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1 slow
clock RC oscillator clock period. If, during the high level period of the slow clock RC oscillator, less
than 8 fast crystal oscillator clock periods have been counted, then a failure is declared.
Ceramic Resonator-based oscillator clock edge and timing logic clocked on the slow clock RC
oscillator controlling the counter. The counter is cleared when the slow clock RC oscillator signal is
low and enabled when the slow clock RC oscillator is high. Thus the failure detection time is 1 slow
clock RC oscillator clock period. If, during the high level period of the slow clock RC oscillator, less
than 8 fast crystal oscillator clock periods have been counted, then a failure is declared.
If a failure of the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is detected, the
CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not
masked. The interrupt remains active until a read operation in the PMC_SR register. The user can
know the status of the clock failure detector at any time by reading the CFDS bit in the PMC_SR
register.
CFDEV flag is set in the PMC Status Register (PMC_SR), and generates an interrupt if it is not
masked. The interrupt remains active until a read operation in the PMC_SR register. The user can
know the status of the clock failure detector at any time by reading the CFDS bit in the PMC_SR
register.
If the 3 to 20 MHz Crystal or Ceramic Resonator-based oscillator clock is selected as the source clock
of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACKor PLLBCK (CSS = 2 or 3), a
clock failure detection automatically forces MAINCK to be the source clock for the master clock
(MCK).Then, regardless of the PMC configuration, a clock failure detection automatically forces the
12/8/4 MHz Fast RC Oscillator to be the source clock for MAINCK. If the Fast RC Oscillator is
disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure
detection mechanism.
of MAINCK (MOSCSEL = 1), and if the Master Clock Source is PLLACKor PLLBCK (CSS = 2 or 3), a
clock failure detection automatically forces MAINCK to be the source clock for the master clock
(MCK).Then, regardless of the PMC configuration, a clock failure detection automatically forces the
12/8/4 MHz Fast RC Oscillator to be the source clock for MAINCK. If the Fast RC Oscillator is
disabled when a clock failure detection occurs, it is automatically re-enabled by the clock failure
detection mechanism.
It takes 2 slow clock RC oscillator cycles to detect and switch from the 3 to 20 MHz Crystal, or
Ceramic Resonator-based Oscillator, to the 12/8/4 MHz Fast RC Oscillator if the Master Clock source
is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACKor PLLBCK.
Ceramic Resonator-based Oscillator, to the 12/8/4 MHz Fast RC Oscillator if the Master Clock source
is Main Clock, or 3 slow clock RC oscillator cycles if the Master Clock source is PLLACKor PLLBCK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator
(PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect
the driven device, if a clock failure is detected.
(PWM) Controller. With this connection, the PWM controller is able to force its outputs and to protect
the driven device, if a clock failure is detected.
The user can know the status of the clock failure detector at any time by reading the FOS bit in the
PMC_SR register.
PMC_SR register.
This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in
the PMC Fault Output Clear Register (PMC_FOCR).
the PMC Fault Output Clear Register (PMC_FOCR).