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ATSAM4S-XPLD
464
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
28.2.13 Programming Sequence
1.
Enabling the Main Oscillator:
The main oscillator is enabled by setting the MOSCXTEN field in the Main Oscillator Register
(CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in
the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the
user must wait for MOSCXTS field in the PMC_SR register to be set. This can be done either
by polling the status register, or by waiting the interrupt line to be raised if the associated inter-
rupt to MOSCXTS has been enabled in the PMC_IER register.
(CKGR_MOR). The user can define a start-up time. This can be achieved by writing a value in
the MOSCXTST field in CKGR_MOR. Once this register has been correctly configured, the
user must wait for MOSCXTS field in the PMC_SR register to be set. This can be done either
by polling the status register, or by waiting the interrupt line to be raised if the associated inter-
rupt to MOSCXTS has been enabled in the PMC_IER register.
2.
Checking the Main Oscillator Frequency (Optional):
In some situations the user may need an accurate measure of the main clock frequency. This
measure can be accomplished via the Main Clock Frequency Register (CKGR_MCFR).
measure can be accomplished via the Main Clock Frequency Register (CKGR_MCFR).
Once the MAINFRDY field is set in CKGR_MCFR, the user may read the MAINF field in
CKGR_MCFR by performing another CKGR_MCFR read access. This provides the number of
main clock cycles within sixteen slow clock cycles.
CKGR_MCFR by performing another CKGR_MCFR read access. This provides the number of
main clock cycles within sixteen slow clock cycles.
3.
Setting PLL and Divider:
All parameters needed to configure PLLA and the divider are located in CKGR_PLLAxR.
The DIV field is used to control the divider itself. It must be set to 1 when PLL is used. By
default, DIV parameter is set to 0 which means that the divider is turned off.
default, DIV parameter is set to 0 which means that the divider is turned off.
The MUL field is the PLL multiplier factor. This parameter can be programmed between 0 and
80. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input
frequency multiplied by (MUL + 1).
80. If MUL is set to 0, PLL will be turned off, otherwise the PLL output frequency is PLL input
frequency multiplied by (MUL + 1).
The PLLCOUNT field specifies the number of slow clock cycles before the LOCK bit is set in
PMC_SR, after CKGR_PLLA(B)R has been written.
PMC_SR, after CKGR_PLLA(B)R has been written.
Once the CKGR_PLL register has been written, the user must wait for the LOCK bit to be set in
the PMC_SR. This can be done either by polling the status register or by waiting the interrupt
line to be raised if the associated interrupt to LOCK has been enabled in PMC_IER. All param-
eters in CKGR_PLLA(B)R can be programmed in a single write operation. If at some stage one
of the following parameters, MUL or DIV is modified, the LOCK bit will go low to indicate that
PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is constrained to
wait for LOCK bit to be set before using the PLL output clock.
the PMC_SR. This can be done either by polling the status register or by waiting the interrupt
line to be raised if the associated interrupt to LOCK has been enabled in PMC_IER. All param-
eters in CKGR_PLLA(B)R can be programmed in a single write operation. If at some stage one
of the following parameters, MUL or DIV is modified, the LOCK bit will go low to indicate that
PLL is not ready yet. When PLL is locked, LOCK will be set again. The user is constrained to
wait for LOCK bit to be set before using the PLL output clock.
4.
Selection of Master Clock and Processor Clock
The Master Clock and the Processor Clock are configurable via the Master Clock Register
(PMC_MCKR).
(PMC_MCKR).
The CSS field is used to select the Master Clock divider source. By default, the selected clock
source is main clock.
source is main clock.
The PRES field is used to control the Master Clock prescaler. The user can choose between
different values (1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to main clock.
different values (1, 2, 3, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by
PRES parameter. By default, PRES parameter is set to 1 which means that master clock is
equal to main clock.
Once PMC_MCKR has been written, the user must wait for the MCKRDY bit to be set in
PMC_SR. This can be done either by polling the status register or by waiting for the interrupt
line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER
register.
PMC_SR. This can be done either by polling the status register or by waiting for the interrupt
line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER
register.
The PMC_MCKR must not be programmed in a single write operation. The preferred program-
ming sequence for PMC_MCKR is as follows:
ming sequence for PMC_MCKR is as follows:
If a new value for CSS field corresponds to PLL Clock,