Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 55

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

EPSR

Access: Read-write

Reset: 0x000000000

The EPSR contains the Thumb state bit, and the execution state bits for either the If-Then (IT) instruction, or the Interruptible-
Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction.

Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write 
the EPSR using the MSR instruction in the application software are ignored. Fault handlers can examine the EPSR value in the 
stacked PSR to indicate the operation that is at fault. See 

When an interrupt occurs during the execution of an LDM, STM, PUSH, POP, VLDM, VSTM, VPUSH,

or VPOP instruction, the processor:

– Stops the load multiple or store multiple instruction operation temporarily

– Stores the next register operand in the multiple operation to EPSR bits[15:12].

After servicing the interrupt, the processor:

– Returns to the register pointed to by bits[15:12]

– Resumes the execution of the multiple load or store instruction.

When the EPSR holds the ICI execution state, bits[26:25,11:10] are zero.

Indicates the execution state bits of the 

IT

 instruction.

The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The con-
ditions for the instructions are either all the same, or some can be the inverse of others. See 

 for more information.

The Cortex-M4 processor only supports the execution of instructions in Thumb state. The following can clear the T bit to 0:

– Instructions BLX, BX and POP{PC}

– Restoration from the stacked xPSR value on an exception return

– Bit[0] of the vector value on an exception entry or reset.

 for more information.

31

30

29

28

27

26

25

24

–

ICI/IT

T

23

22

21

20

19

18

17

16

–

15

14

13

12

11

10

9

8

ICI/IT

–

7

6

5

4

3

2

1

0

–