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ATSAM4S-XPLD
56
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
12.4.1.12Exception Mask Registers
The exception mask registers disable the handling of exceptions by the processor. Disable exceptions where they might
impact on timing critical tasks.
impact on timing critical tasks.
To access the exception mask registers use the MSR and MRS instructions, or the CPS instruction to change the value
of PRIMASK or FAULTMASK. See
of PRIMASK or FAULTMASK. See
12.4.1.13Priority Mask Register
Name:
PRIMASK
Access: Read-write
Reset: 0x000000000
The PRIMASK register prevents the activation of all exceptions with a configurable priority.
• PRIMASK
0: No effect
1: Prevents the activation of all exceptions with a configurable priority.
31
30
29
28
27
26
25
24
–
23
22
21
20
19
18
17
16
–
15
14
13
12
11
10
9
8
–
7
6
5
4
3
2
1
0
–
PRIMASK