Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 606

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. 

This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by
255.

Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. 

At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.

The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip
Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without
reprogramming. 

 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be

programmed to modify the transfer waveforms:



The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the 
Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one.



The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the 
start of SPCK to be delayed after the chip select has been asserted.



The delay between consecutive transfers, independently programmable for each chip select by writing the 
DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select

These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.

MSB

LSB

6

5

4

3

2

1

SPCK

MOSI

(from master)

NPCS0

MSB

LSB

6

5

4

3

2

1

1

2

3

ENDTX

TXEMPTY

MSB

LSB

6

5

4

3

2

1

MSB

LSB

6

5

4

3

2

1

MISO

(from slave)

MSB

LSB

6

5

4

3

2

1

MSB

LSB

6

5

4

3

2

1

ENDRX

TXBUFE

RXBUFF