Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer's size it has
to point to. The PDC will perform the following transfer size depending on the mode and number of bits per data.

Fixed Mode:



8-bit Data:
Byte transfer, PDC Pointer Address = Address + 1 byte,
PDC Counter = Counter - 1



8-bit to 16-bit Data:
2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC Pointer Address = Address + 2 bytes,
PDC Counter = Counter - 1

Variable Mode:

In variable Mode, PDC Pointer Address = Address +4 bytes and PDC Counter = Counter - 1 for 8 to 16-bit transfer size.
When using the PDC, the TDRE and RDRF flags are handled by the PDC, thus the user’s application does not have to
check those bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF), TX Buffer Empty
(TXBUFE) are significant. For further details about the Peripheral DMA Controller and user interface, refer to the PDC
section of the product datasheet.

The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to
NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode
Register (SPI_MR). 

When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one
NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven
low. 

When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the
Mode Register or the Transmit Data Register (depending on PS).

As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any
transfer, only 15 peripherals can be decoded.

The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the
characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded
peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible
peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 

 below shows such an

implementation.

If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This is not
needed for all other chip select lines since Mode Fault Detection is only on NPCS0.