Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 636

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit
slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case
(MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH),
enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.

If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the
master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after
the stop condition. See 

the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.

When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be
set at the same time. See 

. When a multiple data byte read is performed, with or without internal address

. For Internal Address usage see

 

RXRDY is used as Receive Ready for the PDC receive channel.

A

S

DADR

R

DATA

N

P

TXCOMP

Write START

STOP Bit

RXRDY

Read RHR

TWD

N

A

S

DADR

R

DATA n

A

A

DATA (n+1)

A

DATA (n+m)

DATA (n+m)-1

P

TWD

TXCOMP

Write START Bit

RXRDY

Write STOP Bit

after next-to-last data read

Read RHR

DATA n

Read RHR

DATA (n+1)

Read RHR

DATA (n+m)-1

Read RHR

DATA (n+m)