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ATSAM4S-XPLD
638
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 33-12.Master Read with One, Two or Three Bytes Internal Address and One Data Byte
33.8.6.2 10-bit Slave Addressing
For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave
address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and
IADR[23:16] can be used the same as in 7-bit Slave Addressing.
address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and
IADR[23:16] can be used the same as in 7-bit Slave Addressing.
Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10)
1.
Program IADRSZ = 1,
2.
Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3.
Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal
addresses to access the device.
Figure 33-13. Internal Address Usage
33.8.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
33.8.7.1 Data Transmit with the PDC
1.
Initialize the transmit PDC (memory pointers, transfer size).
2.
Configure the master mode.
3.
Start the transfer by setting the PDC TXTEN bit.
4.
Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt.
5.
Disable the PDC by setting the PDC TXDIS bit.
S
DADR
W
A
IADR(23:16)
A
IADR(15:8)
A
IADR(7:0)
A
S
DADR
W
A
IADR(15:8)
A
IADR(7:0)
A
A
IADR(7:0)
A
S
DADR
W
DATA
N
P
Sr
DADR
R
A
Sr
DADR
R
A
DATA
N
P
Sr
DADR
R
A
DATA
N
P
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
T
A
R
T
T
A
R
T
M
S
B
B
Device
Address
0
L
S
B
B
R
/
W
A
C
K
C
K
M
S
B
B
W
R
I
T
E
E
A
C
K
C
K
A
C
K
C
K
L
S
B
B
A
C
K
C
K
FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
DATA
S
T
T
O
P