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Los códigos de productos
ATSAM4S-XPLD
64
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Notes: 1.
See
2.
WT = Write through, no write allocate. WBWA = Write back, write allocate. See the
for more
information.
Instruction Prefetch and Branch Prediction
The Cortex-M4 processor:
Prefetches instructions ahead of execution
Speculatively prefetches from branch target addresses.
12.4.2.4 Software Ordering of Memory Accesses
The order of instructions in the program flow does not always guarantee the order of the corresponding memory
transactions. This is because:
transactions. This is because:
The processor can reorder some memory accesses to improve efficiency, providing this does not affect the
behavior of the instruction sequence.
behavior of the instruction sequence.
The processor has multiple bus interfaces
Memory or devices in the memory map have different wait states
Some memory accesses are buffered or speculative.
of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier
instructions to force that ordering. The processor provides the following memory barrier instructions:
instructions to force that ordering. The processor provides the following memory barrier instructions:
DMB
The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent
memory transactions. See
memory transactions. See
.
DSB
The Data Synchronization Barrier (DSB) instruction ensures that outstanding memory transactions complete before
subsequent instructions execute. See
subsequent instructions execute. See
.
ISB
The Instruction Synchronization Barrier (ISB) ensures that the effect of all completed memory transactions is
recognizable by subsequent instructions. See
recognizable by subsequent instructions. See
MPU Programming
Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by
subsequent instructions.
subsequent instructions.
12.4.2.5 Bit-banding
A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions
occupy the lowest 1 MB of the SRAM and peripheral memory regions.
occupy the lowest 1 MB of the SRAM and peripheral memory regions.
The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions:
0xA0000000-
0xBFFFFFFF
0xBFFFFFFF
External device
-
0xC0000000-
0xDFFFFFFF
0xDFFFFFFF
0xE0000000-
0xE00FFFFF
0xE00FFFFF
Private Peripheral
Bus
Bus
-
0xE0100000-
0xFFFFFFFF
0xFFFFFFFF
Vendor-specific
device
device
-
-
Table 12-5. Memory Region Shareability Policies (Continued)
Address Range
Memory Region
Memory Type
Shareability