Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
Los códigos de productos
ATSAM4S-XPLD
642
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 33-17.TWI Write Operation with Multiple Data Bytes with or without Internal Address
Set the Control register:
- Master enable
TWI_CR = MSEN + SVDIS
Set the Master Mode register:
- Device slave address
- Internal address size
(if IADR used)
- Transfer direction bit
Write ==> bit MREAD = 0
Internal address size = 0
Load Transmit register
TWI_THR = Data to send
Read Status register
TXRDY = 1
Data to send
Read Status register
TXCOMP = 1
END
BEGIN
Set the internal address
TWI_IADR = address
Yes
TWI_THR = data to send
Yes
Yes
Yes
No
No
No
Write STOP Command
TWI_CR = STOP
Set TWI clock
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
(Needed only once)