Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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ATSAM4S-XPLD

640

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Figure 33-15.TWI Write Operation with Single Data Byte without Internal Address

Set TWI clock

(CLDIV, CHDIV, CKDIV) in TWI_CWGR

(Needed only once)

Set the Control register:

- Master enable

TWI_CR = MSEN + SVDIS

Set the Master Mode register:

- Device slave address (DADR)

- Transfer direction bit

Write ==> bit MREAD = 0

Load Transmit register

TWI_THR = Data to send

Read Status register

TXRDY = 1

Read Status register

TXCOMP = 1

Transfer finished

Yes

BEGIN

Write STOP Command

TWI_CR = STOP