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ATSAM4S-XPLD
656
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
33.11 Two-wire Interface (TWI) User Interface
Note:
1. All unlisted offset values are considered as “reserved”.
Table 33-6. Register Mapping
Offset
Register
Name
Access Reset
0x00
Control Register
TWI_CR
Write-only
N / A
0x04
Master Mode Register
TWI_MMR
Read-write
0x00000000
0x08
Slave Mode Register
TWI_SMR
Read-write
0x00000000
0x0C
Internal Address Register
TWI_IADR
Read-write
0x00000000
0x10
Clock Waveform Generator Register
TWI_CWGR
Read-write
0x00000000
0x14 - 0x1C
Reserved
–
–
–
0x20
Status Register
TWI_SR
Read-only
0x0000F009
0x24
Interrupt Enable Register
TWI_IER
Write-only
N / A
0x28
Interrupt Disable Register
TWI_IDR
Write-only
N / A
0x2C
Interrupt Mask Register
TWI_IMR
Read-only
0x00000000
0x30
Receive Holding Register
TWI_RHR
Read-only
0x00000000
0x34
Transmit Holding Register
TWI_THR
Write-only
0x00000000
0xEC - 0xFC
Reserved
–
–
–
0x100 - 0x128
Reserved for PDC registers
–
–
–