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ATSAM4S-XPLD
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Figure 12-5. Little-endian Format
12.4.2.7 Synchronization Primitives
The Cortex-M4 instruction set includes pairs of synchronization primitives. These provide a non-blocking mechanism that
a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a
guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
a thread or process can use to obtain exclusive access to a memory location. The software can use them to perform a
guaranteed read-modify-write memory update sequence, or for a semaphore mechanism.
A pair of synchronization primitives comprises:
A Load-exclusive Instruction, used to read the value of a memory location, requesting exclusive access to that location.
A Store-Exclusive instruction, used to attempt to write to the same memory location, returning a status bit to a register. If
this bit is:
this bit is:
0: It indicates that the thread or process gained exclusive access to the memory, and the write succeeds,
1: It indicates that the thread or process did not gain exclusive access to the memory, and no write is performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
The word instructions LDREX and STREX
The halfword instructions LDREXH and STREXH
The byte instructions LDREXB and STREXB.
The software must use a Load-Exclusive instruction with the corresponding Store-Exclusive instruction.
To perform an exclusive read-modify-write of a memory location, the software must:
1.
Use a Load-Exclusive instruction to read the value of the location.
2.
Update the value, as required.
3.
Use a Store-Exclusive instruction to attempt to write the new value back to the memory location
4.
Test the returned status bit. If this bit is:
0: The read-modify-write completed successfully.
1: No write was performed. This indicates that the value returned at step 1 might be out of date. The software must
retry the read-modify-write sequence.
retry the read-modify-write sequence.
The software can use the synchronization primitives to implement a semaphore as follows:
1.
Use a Load-Exclusive instruction to read from the semaphore address to check whether the semaphore is free.
2.
If the semaphore is free, use a Store-Exclusive instruction to write the claim value to the semaphore address.
3.
If the returned status bit from step 2 indicates that the Store-Exclusive instruction succeeded then the software has
claimed the semaphore. However, if the Store-Exclusive instruction failed, another process might have claimed the
semaphore after the software performed the first step.
claimed the semaphore. However, if the Store-Exclusive instruction failed, another process might have claimed the
semaphore after the software performed the first step.
The Cortex-M4 includes an exclusive access monitor, that tags the fact that the processor has executed a Load-
Exclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory
locations addressed by exclusive accesses by each processor.
Exclusive instruction. If the processor is part of a multiprocessor system, the system also globally tags the memory
locations addressed by exclusive accesses by each processor.
Memory
Register
Address A
A+1
lsbyte
msbyte
A+2
A+3
0
7
B0
B1
B3
B2
31
24 23
16 15
8 7
0
B0
B1
B2
B3