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ATSAM4S-XPLD
676
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 34-9. Character Transmission
34.5.3.3 Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register UART_SR. The
transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written
character is transferred from UART_THR to the Shift Register. The TXRDY bit remains high until a second character is
written in UART_THR. As soon as the first character is completed, the last character written in UART_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
transmission starts when the programmer writes in the Transmit Holding Register (UART_THR), and after the written
character is transferred from UART_THR to the Shift Register. The TXRDY bit remains high until a second character is
written in UART_THR. As soon as the first character is completed, the last character written in UART_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and UART_THR are empty, i.e., all the characters written in UART_THR have been
processed, the TXEMPTY bit rises after the last stop bit has been completed.
processed, the TXEMPTY bit rises after the last stop bit has been completed.
Figure 34-10.Transmitter Control
34.5.4 Peripheral DMA Controller
Both the receiver and the transmitter of the UART are connected to a Peripheral DMA Controller (PDC) channel.
The peripheral data controller channels are programmed via registers that are mapped within the UART user interface
from the offset 0x100. The status bits are reported in the UART status register (UART_SR) and can generate an
interrupt.
from the offset 0x100. The status bits are reported in the UART status register (UART_SR) and can generate an
interrupt.
The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in UART_RHR.
The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of data in UART_THR.
The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of data in UART_THR.
D0
D1
D2
D3
D4
D5
D6
D7
UTXD
Start
Bit
Parity
Bit
Stop
Bit
Example: Parity enabled
Baud Rate
Clock
UART_THR
Shift Register
UTXD
TXRDY
TXEMPTY
Data 0
Data 1
Data 0
Data 0
Data 1
Data 1
S
S
P
P
Write Data 0
in UART_THR
Write Data 1
in UART_THR
stop
stop