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ATSAM4S-XPLD

674

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

Figure 34-4. Character Reception

34.5.2.3 Receiver Ready

When a complete character is received, it is transferred to the UART_RHR and the RXRDY status bit in UART_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register UART_RHR is read.

Figure 34-5. Receiver Ready

34.5.2.4 Receiver Overrun

If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last
transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in UART_SR is set. OVRE is
cleared when the software writes the control register UART_CR with the bit RSTSTA (Reset Status) at 1.

Figure 34-6. Receiver Overrun

34.5.2.5 Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in UART_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
UART_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register UART_CR is
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.

URXD

True Start Detection

Sampling

Parity Bit

Stop Bit

Example: 8-bit, parity enabled 1 stop

1 bit

period

0.5 bit
period

URXD

Read UART_RHR

RXRDY

URXD

RSTSTA

RXRDY

OVRE

stop