Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 707

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity
bit and the receiver does not report any parity error.

 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the

configuration of the USART. Because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a
parity is even.

 

When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR).
The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit to 1. 

 illustrates

the parity bit status setting and clearing.

If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop
Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit to
0 and addresses are transmitted with the parity bit to 1. 

If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and
the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit
to 1. 

To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA to 1. 

The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte
written to US_THR is transmitted as an address. Any character written in US_THR without having written the command
SENDA is transmitted normally with the parity to 0.

A

0x41

0100 0001

1

Odd

A

0x41

0100 0001

0

Even

A

0x41

0100 0001

1

Mark

A

0x41

0100 0001

0

Space

A

0x41

0100 0001

None

None

D0

D1

D2

D3

D4

D5

D6

D7

RXD

Start

Bit

Bad

Parity

Bit

Stop

Bit

Baud Rate

Clock

Write

US_CR

PARE

RXRDY

RSTSTA = 1