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ATSAM4S-XPLD
708
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
35.7.3.10Transmitter Timeguard
The timeguard feature enables the USART interface with slow remote devices.
The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle
state actually acts as a long stop bit.
state actually acts as a long stop bit.
The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When
this field is programmed to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after
each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits.
this field is programmed to zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after
each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits.
, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a
timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard
transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is
completed as the timeguard is part of the current character being transmitted.
transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is
completed as the timeguard is part of the current character being transmitted.
Figure 35-23.Timeguard Operations
indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function
of the Baud Rate.
35.7.3.11Receiver Time-out
The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the
RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can
generate an interrupt, thus indicating to the driver an end of frame.
RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can
generate an interrupt, thus indicating to the driver an end of frame.
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Start
Bit
TG = 4
Write
US_THR
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
TXRDY
TXEMPTY
TG = 4
Table 35-10. Maximum Timeguard Length Depending on Baud Rate
Baud Rate
Bit time
Timeguard
Bit/sec
μs
ms
1 200
833
212.50
9 600
104
26.56
14400 69.4
17.71
19200
52.1
13.28
28800
34.7
8.85
33400
29.9
7.63
56000
17.9
4.55
57600
17.4
4.43
115200
8.7
2.21