Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 766

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined.

The ABETRG bit in the TC_CMR register selects TIOA or TIOB input signal as an external trigger. The ETRGEDG
parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the
external trigger is disabled.

TIOA

RA

RB

Transfer to System Memory

Internal PDC trigger

RA

RB

RA

RB

T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK)

T1

T2

T3

T4

ETRGEDG=3, LDRA=3, LDRB=0, ABETRG=0

TIOB

TIOA

RA

Transfer to System Memory

Internal PDC trigger

RA

RA

T1,T2,T3,T4 = System Bus load dependent (Tmin = 8 MCK)

T1

T2

T3

T4

RA

RA