Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 923

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

PWM_CPRDUPDx [x=0..3]

0x40020210 [0], 0x40020230 [1], 0x40020250 [2], 0x40020270 [3]

Write-only

This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in 

This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform 
period.

Only the first 16 bits (channel counter size) are significant.

If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be 
calculated:

– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,

64, 128, 256, 512, or 1024). The resulting period formula will be:

– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,

respectively:

If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be 
calculated:

– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,

64, 128, 256, 512, or 1024). The resulting period formula will be:

– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,

respectively:

or

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

CPRDUPD

15

14

13

12

11

10

9

8

CPRDUPD

7

6

5

4

3

2

1

0

CPRDUPD

×

(

)

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×

(

)

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×

(

)

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2

×

×

(

)

-------------------------------------------------------

2

×

×

(

)

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2

×

×

(

)

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