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ATSAM4S-XPLD
928
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
39.3
Block Diagram
Figure 39-1. Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit
values to APB registers.
values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain (MCK) and a 48 MHz
clock (UDPCK) used by the 12 MHz domain.
clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then
notified that the device asks for a resume. This optional feature must also be negotiated with the host during the
enumeration.
notified that the device asks for a resume. This optional feature must also be negotiated with the host during the
enumeration.
39.3.1 Signal Description
Atmel Bridge
12 MHz
Suspend/Resume Logic
W
r
a
p
p
e
p
p
e
r
W
r
a
p
p
e
p
p
e
r
U
s
e
e
r
I
I
n
t
e
r
f
f
a
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Serial
Interface
Engine
SIE
MCK
Master Clock
Domain
Domain
Dual
Port
RAM
FIFO
UDPCK
Recovered 12 MHz
Domain
Domain
udp_int
USB Device
Embedded
USB
Transceiver
DDP
DDM
APB
to
MCU
Bus
txoen
eopn
txd
rxdm
rxd
rxdp
Table 39-2. Signal Names
Signal Name
Description
Type
UDPCK
48 MHz clock
input
MCK
Master clock
input
udp_int
Interrupt line connected to the Interrupt Controller
input
DDP
USB D+ line
I/O
DDM
USB D- line
I/O