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ATSAM4S-XPLD
926
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
38.7.43 PWM Channel Dead Time Update Register
Name:
PWM_DTUPDx [x=0..3]
Address:
0x4002021C [0], 0x4002023C [1], 0x4002025C [2], 0x4002027C [3]
Access:
Write-only
This register can only be written if the bits WPSWS4 and WPHWS4 are cleared in
This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the
dead-time values.
dead-time values.
Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant.
• DTHUPD: Dead-Time Value Update for PWMHx Output
Defines the dead-time value for PWMHx output. This value must be defined between 0 and CPRD-CDTY (PWM_CPRx and
PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.
PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.
• DTLUPD: Dead-Time Value Update for PWMLx Output
Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This value is
applied only at the beginning of the next channel x PWM period.
applied only at the beginning of the next channel x PWM period.
31
30
29
28
27
26
25
24
DTLUPD
23
22
21
20
19
18
17
16
DTLUPD
15
14
13
12
11
10
9
8
DTHUPD
7
6
5
4
3
2
1
0
DTHUPD