Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 95

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The table below shows the ranges of offset for immediate, pre-indexed and post-indexed forms.

Restrictions

For load instructions:



Rt can be SP or PC for word loads only



Rt must be different from Rt2 for two-word loads



Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

When Rt is PC in a word load instruction:



Bit[0] of the loaded value must be 1 for correct execution



A branch occurs to the address created by changing bit[0] of the loaded value to 0



If the instruction is conditional, it must be the last instruction in the IT block.

For store instructions:



Rt can be SP for word stores only



Rt must not be PC



Rn must not be PC



Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms.

Condition Flags

These instructions do not change the flags.

Examples 

LDR

R8, [R10]

; Loads R8 from the address in R10.

LDRNE

R2, [R5, #960]!

; Loads (conditionally) R2 from a word

; 960 bytes above the address in R5, and

; increments R5 by 960.

STR

R2, [R9,#const-struc]

; const-struc is an expression evaluating

; to a constant in the range 0-4095.

STRH

R3, [R4], #4

; Store R3 as halfword data into address in

; R4, then increment R4 by 4

LDRD

R8, R9, [R3, #0x20]

; Load R8 from a word 32 bytes above the

; address in R3, and load R9 from a word 36

; bytes above the address in R3

STRD

R0, R1, [R8], #-16

; Store R0 to address in R8, and store R1 to

; a word 4 bytes above the address in R8,

; and then decrement R8 by 16.

Load and Store with register offset.

Syntax

op{type}{cond} Rt, [Rn, Rm {, LSL #n}]

where:

op

is one of:

Word, halfword, signed 
halfword, byte, or signed byte

-255 to 4095

-255 to 255

-255 to 255

Two words

multiple of 4 in the 
range -1020 to 
1020 

multiple of 4 in the 
range -1020 to 
1020 

multiple of 4 in the 
range -1020 to 1020