Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 96

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

LDR

Load Register.

STR

Store Register.

type

is one of:

B

unsigned byte, zero extend to 32 bits on loads.

SB

signed byte, sign extend to 32 bits (LDR only).

H

unsigned halfword, zero extend to 32 bits on loads.

SH

signed halfword, sign extend to 32 bits (LDR only).

-

omit, for word.

cond

Rt

is the register to load or store.

Rn

is the register on which the memory address is based.

Rm

is a register containing a value to be used as the offset.

LSL #n

is an optional shift, with n in the range 0 to 3.

Operation

LDR instructions load a register with a value from memory.

STR instructions store a register value into memory.

The memory address to load from or store to is at an offset from the register Rn. The offset is specified by the register
Rm and can be shifted left by up to 3 bits using LSL.

The value to load or store can be a byte, halfword, or word. For load instructions, bytes and halfwords can either be
signed or unsigned. See 

Restrictions

In these instructions:



Rn must not be PC



Rm must not be SP and must not be PC



Rt can be SP only for word loads and word stores



Rt can be PC only for word loads.

When Rt is PC in a word load instruction:



Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address



If the instruction is conditional, it must be the last instruction in the IT block.

Condition Flags

These instructions do not change the flags.

Examples

STR

R0, [R5, R1]

; Store value of R0 into an address equal to

; sum of R5 and R1

LDRSB

R0, [R5, R1, LSL #1] ; Read byte value from an address equal to

; sum of R5 and two times R1, sign extended it

; to a word value and put it in R0

STR

R0, [R1, R2, LSL #2] ; Stores R0 to an address equal to sum of R1

; and four times R2