Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 99

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

When Rt is PC in a word load instruction:



Bit[0] of the loaded value must be 1 for correct execution, and a branch occurs to this halfword-aligned address



If the instruction is conditional, it must be the last instruction in the IT block.

Condition Flags

These instructions do not change the flags.

Examples

LDR

R0, LookUpTable

; Load R0 with a word of data from an address

; labelled as LookUpTable

LDRSB

R7, localdata

; Load a byte value from an address labelled

; as localdata, sign extend it to a word

; value, and put it in R7

Load and Store Multiple registers.

Syntax

op{addr_mode}{cond} Rn{!}, reglist

where:

op

is one of:

LDM

Load Multiple registers.

STM

Store Multiple registers.

addr_mode

is any one of the following:

IA

Increment address After each access. This is the default.

DB

Decrement address Before each access.

cond

Rn

is the register on which the memory addresses are based. 

!

is an optional writeback suffix. 
If ! is present, the final address, that is loaded from or stored to, is written back into Rn.

reglist

is a list of one or more registers to be loaded or stored, enclosed in braces. It
can contain register ranges. It must be comma separated if it contains more
than one register or register range, see 

LDM and LDMFD are synonyms for LDMIA. LDMFD refers to its use for popping data from Full Descending stacks.

LDMEA is a synonym for LDMDB, and refers to its use for popping data from Empty Ascending stacks.

STM and STMEA are synonyms for STMIA. STMEA refers to its use for pushing data onto Empty Ascending stacks.

STMFD is s synonym for STMDB, and refers to its use for pushing data onto Full Descending stacks

Operation

LDM instructions load the registers in reglist with word values from memory addresses based on Rn.

STM instructions store the word values in the registers in reglist to memory addresses based on Rn.

For LDM, LDMIA, LDMFD, STM, STMIA, and STMEA the memory addresses used for the accesses are at 4-byte
intervals ranging from Rn to Rn + 4 * (n-1), where n is the number of registers in reglist. The accesses happens in order
of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest
number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is
written back to Rn.

For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging
from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist. The accesses happen in order of decreasing