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ATSAM4S-XPLD
990
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
41.6.9 Input Gain and Offset
The ADC has a built in Programmable Gain Amplifier (PGA) and Programmable Offset.
The Programmable Gain Amplifier can be set to gains of 1/2, 1, 2 and 4. The Programmable Gain Amplifier can be used
either for single ended applications or for fully differential applications.
either for single ended applications or for fully differential applications.
If ANACH is set in ADC_MR the ADC can apply different gain and offset on each channel. Otherwise the parameters of
CH0 are applied to all channels.
CH0 are applied to all channels.
The gain is configurable through the GAIN bit of the Channel Gain Register (ADC_CGR) as shown in
To allow full range, analog offset of the ADC can be configured by the OFFSET bit of the Channel Offset Register
(ADC_COR). The Offset is only available in Single Ended Mode.
(ADC_COR). The Offset is only available in Single Ended Mode.
AD10
CH10
AD11
CH11
AD12
CH12
AD13
CH13
AD14
CH14
AD15
CH15
Table 41-5. Input Pins and Channel Number In Differential Mode
Input Pins
Channel Number
AD0-AD1
CH0
AD2-AD3
CH2
AD4-AD5
CH4
AD6-AD7
CH6
AD8-AD9
CH8
AD10-AD11
CH10
AD12-AD13
CH12
AD14-AD15
CH14
Table 41-4. Input Pins and Channel Number in Single Ended Mode (Continued)
Input Pins
Channel Number
Table 41-6. Gain of the Sample and Hold Unit: GAIN Bits and DIFF Bit.
GAIN<0:1>
GAIN (DIFF = 0)
GAIN (DIFF = 1)
00
1
0.5
01
1
1
10
2
2
11
4
2
Table 41-7. Offset of the Sample and Hold Unit: OFFSET DIFF and Gain (G)
OFFSET Bit
OFFSET (DIFF = 0)
OFFSET (DIFF = 1)
0
0
0
1
(G-1)Vrefin/2