Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

When the gain, offset or differential input parameters of the analog cell change between two channels, the analog cell
may need a specific settling time before starting the tracking phase. In that case, the controller automatically waits during
the settling time defined in the 

Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to
program a precise value in the TRACKTIM field. See the product ADC Characteristics section.

The ADC features an automatic calibration (AUTOCALIB) mode for gain errors (calibration).

The automatic calibration sequence can be started at any time writing to '1' the AUTOCAL bit of the ADC Control
Register. The automatic calibration sequence requires a software reset command (SWRST in the ADC_CR register)
prior to write AUTOCAL bit. The end of calibration sequence is given by the EOCAL bit in the interrupt status register
(ADC_ISR), and an interrupt is generated if EOCAL interrupt has been enabled (ADC_IER register).

The calibration sequence will perform an automatic calibration on all enabled channels. The channels required for
conversion do not need to be all enabled during the calibration process if they are programmed with the same gain. Only
channels with different gain settings need to be enabled. The gain settings of all enabled channels must be set before
starting the AUTOCALIB sequence. If the gain settings (ADC_CGR and ADC_COR registers) for a given channel are
changed, the AUTOCALIB sequence must then be started again.

The calibration data (on one or more enabled channels) is stored in the internal ADC memory.

Then, when a new conversion is started (on one or more enabled channels), the converted value (in ADC_LCDR or
ADC_CDRx registers) is a calibrated value. 

Autocalibration is for settings, not for channels. Therefore, if a specific combination of gain has been already calibrated,
and a new channel with the same settings is enabled after the initial calibration, there is no need to restart a calibration. If
different enabled channels have different gain settings, the corresponding channels must be enabled before starting the
calibration.

If a software reset is performed (SWRST bit in ADC_CR) or after power up (or wake-up from Backup mode), the
calibration data in the ADC memory is lost.

Changing the ADC running mode (in ADC_CR register) does not affect the calibration data.

Changing the ADC reference voltage (ADVREF pin) requires a new calibration sequence.

For calibration time, gain error after calibration, refer to the 12-bit ADC electrical characteristics section of the product.

The PDC read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data read to PDC buffer, carried on a
half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register, the 4 most
significant bits are carrying the channel number thus allowing an easier post-processing in the PDC buffer or better
checking the PDC buffer integrity.

The ADC Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted according
to the configuration of ADC_EMR (Extended Mode Register) and ADC_CWR (Compare Window Register) and
converted values. When the Compare occurs, the ADC fault output generates a pulse of one Master Clock Cycle to the
PWM fault input. This fault line can be enabled or disabled within PWM. Should it be activated and asserted by the ADC
Controller, the PWM outputs are immediately placed in a safe state (pure combinational path). Note that the ADC fault
output connected to the PWM is not the COMPE bit. Thus the Fault Mode (FMOD) within the PWM configuration must be
FMOD = 1.