Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos

398

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

indicating data are needed for transmit. If not acknowledge is sent, the I

2

C slave will wait for a new start condition and 

address match.

Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I

2

C slave 

command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on 
the STATUS.DIR bit.

Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.

The STATUS.DIR bit is cleared, indicating an I

2

C master write operation. The SCL line is forced low, stretching the bus 

clock. If an ACK is sent, the I

2

C slave will wait for data to be received. Data, repeated start or stop can be received.

If not acknowledge is sent, the I

2

C slave will wait for a new start condition and address match.

Typically, software will immediately acknowledge the address packet by sending an ACK/NACK bit. The I

2

C slave 

command CTRLB.CMD = 3 can be used for both read and write operation as the command execution is dependent on 
STATUS.DIR.

Writing a one to INTFLAG.AMATCH will also cause an ACK/NACK to be sent corresponding to the CTRLB.ACKACT bit.

After the I

2

C slave has received an address packet, it will respond according to the direction either by waiting for the data 

packet to be received or by starting to send a data packet by writing to DATA.DATA. When a data packet is received or 
sent, INTFLAG.DRDY will be set. Then, if the I

2

C slave was receiving data, it will send an acknowledge according to 

CTRLB.ACKACT.

INTFLAG.DRDY is set, and SCL is held low pending SW interaction.

When a byte transmission is successfully completed, the INTFLAG.DRDY interrupt flag is set. If NACK is received, the 
I

2

C slave must expect a stop or a repeated start to be received. The I

2

C slave must release the data line to allow the I

2

C 

master to generate a stop or repeated start. 

Upon stop detection, the Stop Received bit in the Interrupt Flag register (INTFLAG.PREC) will be set and the I

2

C slave 

will return to the idle state.

The I

2

C hardware incorporates hardware SCL low time-out, which allows a time-out to occur if the clock line is held low 

too long. This time-out is driven by the GCLK_SERCOM_SLOW clock. The GCLK_SERCOM_SLOW clock is used to 
accurately time the time-out and must be configured to used a 32kHz oscillator. The I

2

C interface also allows for a 

SMBus compatible SDA hold time.

The I

2

C interface incorporates a special smart mode that simplifies application code and minimizes the user interaction 

needed to keep hold of the I

2

C protocol. The smart mode accomplishes this by letting the reading of DATA.DATA 

automatically issue an ACK or NACK based on the state of CTRLB.ACKACT.

Setting the Pin Usage bit in the Control A register (CTRLA.PINOUT) for master or slave to 4-wire mode enables 
operation as shown in 

. In this mode, the internal I

2

C tri-state drivers are bypassed, and an external, I

2

C-

compliant tri-state driver is needed when connecting to an I

2

C bus.