Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Hoja De Datos

399

Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

Setting the Quick Command Enable bit in the Control B register (CTRLB.QCEN) enables quick command. When quick 
command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. At 
this point, the software can either issue a stop command or a repeated start by writing CTRLB.CMD or ADDR.ADDR.

The I

2

C slave has the following interrupt sources: 

z

Data Ready 

z

Address Match 

z

Stop Received 

The I

2

C master has the following interrupt sources: 

z

Slave on Bus 

z

Master on Bus 

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear 
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one 
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the 
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled or the I

2

C is reset. See 

 for details on how to clear interrupt flags. 

The I

2

C has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine 

which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 

During I

2

C master operation, the generic clock (GCLK_SERCOMx_CORE) will continue to run in idle sleep mode. If the 

Run In Standby bit in the Control A register (CTRLA.RUNSTDBY) is one, the GLK_SERCOMx_CORE will also run in 
standby sleep mode. Any interrupt can wake up the device.

If CTRLA.RUNSTDBY is zero during I

2

C master operation, the GLK_SERCOMx_CORE will be disabled when an 

ongoing transaction is finished. Any interrupt can wake up the device.

During I

2

C slave operation, writing a one to CTRLA.RUNSTDBY will allow the Address Match interrupt to wake up the 

device. 

In I

2

C slave operation, all receptions will be dropped when CTRLA.RUNSTDBY is zero. 

SCL/SDA

 

pad

I2C

 

Driver

SCL_OUT/

 

SDA_OUT

 

pad

PINOUT

PINOUT

SCL_IN/
SDA_IN

SCL_OUT/
SDA_OUT