STMicroelectronics L6227 DMOS Evaluation Board EVAL6227PD EVAL6227PD Hoja De Datos
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EVAL6227PD
Application information
L6227
22/32
DocID9453 Rev 2
8 Application
information
A typical application using the L6227 device is shown in
. Typical component
values for the application are shown in Table 3. A high quality ceramic capacitor in the range
of 100 to 200 nF should be placed between the power pins (VS
of 100 to 200 nF should be placed between the power pins (VS
A
and VS
B
) and ground near
the L6227 to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitors connected from the EN
frequency transients generated by the switching. The capacitors connected from the EN
A
and EN
B
inputs to ground set the shutdown time for the bridge A and bridge B respectively
when an overcurrent is detected (see
).
The two current sensing inputs (SENSE
A
and SENSE
B
) should be connected to the sensing
resistors with a trace length as short as possible in the layout. The sense resistors should be
non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise
immunity, unused logic pins (except EN
non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise
immunity, unused logic pins (except EN
A
and EN
B
) are best connected to 5 V (high logic
level) or GND (low logic level) (see
). It is recommended
to keep power ground and signal ground separated on the PCB.
Table 8. Component values for typical application
Component
Value
C
1
100
F
C
2
100 nF
C
A
1 nF
C
B
1 nF
C
BOOT
220 nF
C
P
10 nF
C
ENA
5.6 nF
C
ENB
5.6 nF
C
REFA
68 nF
C
REFB
68 nF
D
1
1N4148
D
2
1N4148
R
A
39 K
R
B
39 K
R
ENA
100 K
R
ENB
100 K
R
P
100
R
SENSEA
0.6
R
SENSEB
0.6