Intel S5500WBR Manual De Usuario
Functional Architecture
Intel® Server Board S5500WB TPS
36
Revision 1.9
Intel order number E53971-008
The Intel
®
Server Board S5500WB provides a mechanism to support video to the front panel
via the use of an internal header. When a monitor is plugged into the front panel video
connector, the rear panel video stream is disconnected.
connector, the rear panel video stream is disconnected.
There is a jumper option to change this default action. When the internal header is used by a
third-party Management card to do KVM over LAN and then when a monitor is plugged into the
rear panel video connector, the video stream to the internal header is cut off.
third-party Management card to do KVM over LAN and then when a monitor is plugged into the
rear panel video connector, the video stream to the internal header is cut off.
3.13 I/O Slots
3.13.1 X16 Riser Slot Definition
Slot 6 was defined to support riser cards. Slot 6 has a x16 physical connector with a PCI
Express* Gen II x8 electrical interface. Two clocks are provided so the bus can be bifurcated
into two x4 connectors.
Express* Gen II x8 electrical interface. Two clocks are provided so the bus can be bifurcated
into two x4 connectors.
Because of CPU placement, a 1U system supports only PCI Express* adapters that meet the
PCI SIG half card definition. Full-length boards are supported in a 2U system by using a taller
riser and extending the board over the 1U CPU heatsinks or if CPU2 is unpopulated.
PCI SIG half card definition. Full-length boards are supported in a 2U system by using a taller
riser and extending the board over the 1U CPU heatsinks or if CPU2 is unpopulated.
Appendix A describes the pin assignments for this connector.
3.13.2 PE WIDTH Strapping
On the Intel
®
Server Board S5500WB, the IOH needs to be informed of the PCI Express* bus
width during power on. This is accomplished using the PEWIDTH input straps. The mechanism
used is the PEWIDTH bits, one bit is used to signify the width and number of PCI Express*
buses used by the riser. For slot 6, the PEWIDTH bit used is 0.
used is the PEWIDTH bits, one bit is used to signify the width and number of PCI Express*
buses used by the riser. For slot 6, the PEWIDTH bit used is 0.
Table 11. PEWIDTH Strapping Bits
Riser
Description
PEWIDTH0
pin A50
1U one x8
1 x8 PCI Express* Slot
0
2U two x4
2 X4 PCI Express* Slots
1
By using this mechanism for selecting PCI Express* port width, you can avoid a BIOS
rediscover and reboot.
rediscover and reboot.
The PEWIDTH is pulled up to 3.3 V Aux on the baseboard and grounded, if necessary, by the
riser. The baseboard provides an inverter and voltage level translator before passing this signal
to the IOH.
riser. The baseboard provides an inverter and voltage level translator before passing this signal
to the IOH.
3.13.3 Slot 1 PCI Express* x8 Connector
Slot 1 provides a PCI Express* x4 bus on an x8 connector, if provided, for use in a 2U chassis
that uses LP boards without risers. Although it is feasible to use the IOM at the same time, it
would require 2U chassis back panel changes.
that uses LP boards without risers. Although it is feasible to use the IOM at the same time, it
would require 2U chassis back panel changes.