Intel C2518 FH8065501516710 Hoja De Datos
Los códigos de productos
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
93
Volume 2—System Agent and Root Complex—C2000 Product Family
Global Error Reporting
4.7.7.2
Global Error Registers
The global error registers collect the errors reported by the local interface and convert
the error to system events.
• Global Error Mask/Status Register
The SoC provides three global error status registers to collect the errors
reported by the SoC clusters—Global Fatal Error Status (GFERRSTS), Global
Non-Fatal Error (GNERRSTS) Status, and Global Correctable Error Status
(GCORERRSTS). Each register has an identical format that each bit in the
register represents the fatal, non-fatal, or correctable error reported by its
associated interface: memory controller, SoC system agent, PCIe Root Ports,
and Root Complex Event Collector (RCEC) logic. Local clusters map the
detected errors to three error classes and report them to the global error logic.
These errors are sorted into fatal, non-fatal, and correctable, and reported to
the respective global error status registers. When an error is reported by the
local cluster, the corresponding bit in the Global Fatal, Non-Fatal or Correctable
Error Status register is set. The software clears the error bit by writing 1 to the
bit. Each error is individually masked by the global error control registers. If an
error is masked, the corresponding status bit is not set for any subsequent
reported error. The Global Error Mask register is non-sticky and cleared by
reset.
• Global Log Registers
• Global System Event Register
The errors collected by the global error registers are mapped to system events.
The System Event Status bit reflects the logical OR output of all associated
error severity unmasked errors. Each System Event Status bit individually
masks by the System Event Control registers. Masking a System Event Status
bit forces the corresponding bit to 0. When a System Event Status bit
transitions from 0 to 1, the bit triggers one or more system events based on
the programming of the System Event Map register as shown in
.
Each error class is associated with one of the system events: SMI or NMI.