Philips 8-bit microcontroller with two-clock 80C51 core UM10109 Manual De Usuario

User manual

Rev. 02 — 23 May 2005

103 of 133

Philips Semiconductors

UM10109

P89LPC932A1 User manual

15.4 Watchdog Timer in Timer mode

Figure 49

shows the Watchdog Timer in Timer Mode. In this mode, any changes to

WDCON are written to the shadow register after one watchdog clock cycle. A watchdog
underflow will set the WDTOF bit. If IEN0.6 is set, the watchdog underflow is enabled to
cause an interrupt. WDTOF is cleared by writing a logic 0 to this bit in software. When an
underflow occurs, the contents of WDL is reloaded into the down counter and the
watchdog timer immediately begins to count down again.

A feed is necessary to cause WDL to be loaded into the down counter before an underflow
occurs. Incorrect feeds are ignored in this mode.

Fig 48. Watchdog Timer in Watchdog Mode (WDTE = 1).

PRE2

PRE1

PRE0

WDRUN

WDTOF

WDCLK

WDCON (A7H)

SHADOW REGISTER

PRESCALER

002aaa905

8-BIT DOWN

COUNTER

WDL (C1H)

watchdog

oscillator

PCLK

÷32

MOV WFEED1, #0A5H
MOV WFEED2, #05AH

reset (1)

Fig 49. Watchdog Timer in Timer Mode (WDTE = 0).