Philips 8-bit microcontroller with two-clock 80C51 core UM10109 Manual De Usuario
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 02 — 23 May 2005
47 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
9.1 CCU Clock (CCUCLK)
The CCU runs on the CCUCLK, which can be either PCLK in basic timer mode or the
output of a PLL (see
output of a PLL (see
). The PLL is designed to use a clock source between
0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and
32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider
(PLLDV3:0 bits in the TCR21 register) to help divide PCLK into a frequency between
0.5 MHz and 1 MHz
32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider
(PLLDV3:0 bits in the TCR21 register) to help divide PCLK into a frequency between
0.5 MHz and 1 MHz
9.2 CCU Clock prescaling
This CCUCLK can further be divided down by a prescaler. The prescaler is implemented
as a 10-bit free-running counter with programmable reload at overflow. Writing a value to
the prescaler will cause the prescaler to restart.
as a 10-bit free-running counter with programmable reload at overflow. Writing a value to
the prescaler will cause the prescaler to restart.
9.3 Basic timer operation
The Timer is a free-running up/down counter counting at the pace determined by the
prescaler. The timer is started by setting the CCU Mode Select bits TMOD21 and
TMOD20 in the CCU Control Register 0 (TCR20) as shown in the table in the TCR20
register description (
prescaler. The timer is started by setting the CCU Mode Select bits TMOD21 and
TMOD20 in the CCU Control Register 0 (TCR20) as shown in the table in the TCR20
register description (
).
The CCU direction control bit, TDIR2, determines the direction of the count. TDIR2 = 0:
Count up, TDIR2 = 1: Count down. If the timer counting direction is changed while the
counter is running, the count sequence will be reversed in the CCUCLK cycle following the
write of TDIR2. The timer can be written or read at any time and newly-written values will
take effect when the prescaler overflows. The timer is accessible through two SFRs,
TL2(low byte) and TH2(high byte). A third 16-bit SFR, TOR2H:TOR2L, determines the
overflow reload value. TL2, TH2 and TOR2H, TOR2L will be 0 after a reset
Count up, TDIR2 = 1: Count down. If the timer counting direction is changed while the
counter is running, the count sequence will be reversed in the CCUCLK cycle following the
write of TDIR2. The timer can be written or read at any time and newly-written values will
take effect when the prescaler overflows. The timer is accessible through two SFRs,
TL2(low byte) and TH2(high byte). A third 16-bit SFR, TOR2H:TOR2L, determines the
overflow reload value. TL2, TH2 and TOR2H, TOR2L will be 0 after a reset
Fig 20. Capture Compare Unit block diagram.
16-BIT SHADOW REGISTER
TOR2H TO TOR2L
16-BIT SHADOW REGISTER
OCRxH TO OCRxL
16-BIT CAPTURE
REGISTER ICRxH, L
INTERRUPT FLAG
TICF2x SET
EVENT
COUNTER
NOISE
FILTER
ICNFx
EDGE
SELECT
ICESx
16-BIT COMPARE
VALUE
TIMER > COMPARE
16-BIT TIMER RELOAD
REGISTER
16-BIT UP/DOWN TIMER
WITH RELOAD
FCOx
OCA
ICA
ICB
OCB
OVERFLOW/
UNDERFLOW
OCC
OCD
COMPARE CHANNELS A TO D
CAPTURE CHANNELS A, B
002aab009
10-BIT DIVIDER
32
× PLL
4-BIT
DIVIDER