Philips 8-bit microcontroller with two-clock 80C51 core UM10109 Manual De Usuario
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 02 — 23 May 2005
95 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
13.2 Internal reference voltage
An internal reference voltage, Vref, may supply a default reference when a single
comparator input pin is used. Please refer to the P89LPC932A1 data sheet for
specifications
comparator input pin is used. Please refer to the P89LPC932A1 data sheet for
specifications
13.3 Comparator input pins
Comparator input and reference pins maybe be used as either digital I/O or as inputs to
the comparator. When used as digital I/O these pins are 5 V tolerant. However, when
selected as comparator input signals in CMPn lower voltage limits apply. Please refer to
the P89LPC932A1 data sheet for specifications.
the comparator. When used as digital I/O these pins are 5 V tolerant. However, when
selected as comparator input signals in CMPn lower voltage limits apply. Please refer to
the P89LPC932A1 data sheet for specifications.
13.4 Comparator interrupt
Each comparator has an interrupt flag CMFn contained in its configuration register. This
flag is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt. The two comparators use one common
interrupt vector. The interrupt will be generated when the interrupt enable bit EC in the
IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register.
If both comparators enable interrupts, after entering the interrupt service routine, the user
will need to read the flags to determine which comparator caused the interrupt.
flag is set whenever the comparator output changes state. The flag may be polled by
software or may be used to generate an interrupt. The two comparators use one common
interrupt vector. The interrupt will be generated when the interrupt enable bit EC in the
IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register.
If both comparators enable interrupts, after entering the interrupt service routine, the user
will need to read the flags to determine which comparator caused the interrupt.
When a comparator is disabled the comparator’s output, COx, goes high. If the
comparator output was low and then is disabled, the resulting transition of the comparator
output from a low to high state will set the comparator flag, CMFx. This will cause an
interrupt if the comparator interrupt is enabled. The user should therefore disable the
comparator interrupt prior to disabling the comparator. Additionally, the user should clear
the comparator flag, CMFx, after disabling the comparator.
comparator output was low and then is disabled, the resulting transition of the comparator
output from a low to high state will set the comparator flag, CMFx. This will cause an
interrupt if the comparator interrupt is enabled. The user should therefore disable the
comparator interrupt prior to disabling the comparator. Additionally, the user should clear
the comparator flag, CMFx, after disabling the comparator.
13.5 Comparators and power reduction modes
Either or both comparators may remain enabled when Power-down mode or Idle mode is
activated, but both comparators are disabled automatically in Total Power-down mode.
activated, but both comparators are disabled automatically in Total Power-down mode.
If a comparator interrupt is enabled (except in Total Power-down mode), a change of the
comparator output state will generate an interrupt and wake-up the processor. If the
comparator output to a pin is enabled, the pin should be configured in the push-pull mode
in order to obtain fast switching times while in Power-down mode. The reason is that with
the oscillator stopped, the temporary strong pull-up that normally occurs during switching
on a quasi-bidirectional port pin does not take place.
comparator output state will generate an interrupt and wake-up the processor. If the
comparator output to a pin is enabled, the pin should be configured in the push-pull mode
in order to obtain fast switching times while in Power-down mode. The reason is that with
the oscillator stopped, the temporary strong pull-up that normally occurs during switching
on a quasi-bidirectional port pin does not take place.
Comparators consume power in Power-down mode and Idle mode, as well as in the
normal operating mode. This should be taken into consideration when system power
consumption is an issue. To minimize power consumption, the user can power-down the
comparators by disabling the comparators and setting PCONA.5 to logic 1, or simply
putting the device in Total Power-down mode.
normal operating mode. This should be taken into consideration when system power
consumption is an issue. To minimize power consumption, the user can power-down the
comparators by disabling the comparators and setting PCONA.5 to logic 1, or simply
putting the device in Total Power-down mode.