Fisher & Paykel MR730 Manual De Usuario

9

Ref. 185040646 MR730/720/700/480 Technical Manual ¯ Revision F ¯ Issued March 2001

This section describes briefly the operation of each of the circuit sections. Refer to the circuit diagrams in § 8.5 to 8.8.

The one basic control board, with various discreet hardware changes, provides the controlling functions for the
MR730/720/700/480 range of humidifiers. Each model however is controlled by a unique software version.

Three standard characteristic thermistors control all temperature functions:

•

One thermistor is mounted in a probe at the end of the delivery hose to measure delivered airway temperature
(connector J4-1,3). This temperature is indicated by the digital display on the humidifier front panel.

•

A second thermistor mounted in a probe measures the chamber temperature at the top of the humidifying
chamber (connector J4-2,3). In heater wire mode this thermistor is used to monitor and control the chamber
outlet temperature.

•

A third thermistor is permanently mounted in intimate contact with the heaterplate (HP) (connector J3-1,3). This
prevents excessive heaterplate temperatures during a warm up cycle.

The 1 by 8 analog switch (U8) selects under processor control (PB0-3) various input signals and reference potentials.
Selected sequentially are potentials giving; (0-3): the position of the temperature set potentiometer VR3, and offset
potentiometer VR2. (4-6): calibration temperatures of 9, 34.5 and 60 °C across resistors R18, R17 and R16, and from (7):
the heaterplate (HP) thermistor.

From the 3 by 2 analog switch (U9) under processor control (PB4-6) the airway temperature and the chamber outlet
temperatures from the dual probe temperature sensor are also read.

The temperature probe inputs are filtered by the C30, C31, R28, R26, C19, C20 network for EMI suppression. The selected
output of the analog switch network U8, U9 is fed to pin 10 of U10d, a low pass operational amplifier with a gain of 11.
This stage is filtered with C23 to give protection from any voltage transients appearing at its input. The integrating stage
U10b rests for most of the time (50 to 60ms) with R35 connected (through an analog switch in U9) across the integrating
capacitor C22 holding it in a discharged state. With VR5 and R34 connected to the non-inverting input of U10b the stage
has a ‘static' gain of about 0.5 giving a resting level of about -2.5 to -3 V at the output pin 1.

Under processor control (PB6) when the switch section of U9 across C22 is opened the output of U10b ramps up (0.1-5
ms). This rising ramp voltage is fed via R36 to the comparator stage U10e where it is referenced via R41 to the output
voltage level of U10d. When the ramp voltage exceeds the threshold level of U10d the output of the comparator stage
U10e switches high. This fast rising edge, assisted by the speed up capacitor C24, is fed to the RST 6.5 interrupt input of
U3.

After selecting one of the 10 input signals through the switch network of U8, U9 there is a 50 to 60ms pause to allow
U10d to settle. At this point the switch across the integrator U10b is opened initiating a linear ramp output and the 14 bit
counter in U4 is started. Within a time period of 100 ns to 5 ms the ramp will cause a RST6.5 interrupt to occur. The
processor on responding to the interrupt, first stops the counter, then closes the switch across the integrator readying it
for the next cycle. The input switch network U8, U9 can now be stepped to the next input. The 14 bit counter can now be
read and its value equated to the input signal. In this way all 10 input channels are continuously scanned. VR5 is set