Fisher & Paykel MR730 Manual De Usuario
10
Ref. 185040646 MR730/720/700/480 Technical Manual ¯ Revision F ¯ Issued March 2001
during calibration to give the desired ramp rate. Thus all points are scanned once every 500 to 600 ms, self calibration
performed, and the digital display updated.
performed, and the digital display updated.
4.2.5
P
OWER
L
INE
I
NTERRUPT
(R
EVISIONS
D/F PCB
S
)
A sample of the power supply frequency is derived from the power transformer 22 Vac secondary via R56 and Q1,
buffered by Schmitt trigger U5f and fed to the RST7.5 interrupt of U3. The operating software determines the supply
frequency facilitating the generation of a real time clock and also enabling a zero crossing detector for triac switching.
The ADC is also phase synchronised with the line frequency thus eliminating any common error from this source.
buffered by Schmitt trigger U5f and fed to the RST7.5 interrupt of U3. The operating software determines the supply
frequency facilitating the generation of a real time clock and also enabling a zero crossing detector for triac switching.
The ADC is also phase synchronised with the line frequency thus eliminating any common error from this source.
4.2.6
P
OWER
L
INE
I
NTERRUPT
(R
EVISION
H PCB
AND LATER
)
The zero crossing is derived from the 10 Vac secondary. Resistor R61 ensures that the secondary is ground referenced
when the diodes D13 to D16 are not conducting. Network R1, R69, and C2 removes any unwanted noise from the zero
crossing circuit. The operating software determines the supply frequency facilitating the generation of a real time clock
and also enabling a zero crossing detector for triac switching. The ADC is also phase synchronised with the line
frequency thus eliminating any common error from this source.
when the diodes D13 to D16 are not conducting. Network R1, R69, and C2 removes any unwanted noise from the zero
crossing circuit. The operating software determines the supply frequency facilitating the generation of a real time clock
and also enabling a zero crossing detector for triac switching. The ADC is also phase synchronised with the line
frequency thus eliminating any common error from this source.
4.2.7
41 °C C
OMPARATOR
Operational amplifier U10c is a protection circuit to sense excessive delivery temperature rise. The non inverting input
pin 5 is connected directly (via connector J4-1) to the patient airway thermistor. The inverting input goes to an
adjustable divider network R32, VR4, R33. VR4 is set during calibration to ensure that the output pin 7 of U10c is low
above an input temperature of 41 °C. This low output (OVHT) is fed via the isolating diode resistor networks D19, R55
and D20, R61 to clamp the bases of switching transistors Q10 and Q12. In this way, a patient airway temperature greater
than 41 °C causes both heaters to be shut down.
pin 5 is connected directly (via connector J4-1) to the patient airway thermistor. The inverting input goes to an
adjustable divider network R32, VR4, R33. VR4 is set during calibration to ensure that the output pin 7 of U10c is low
above an input temperature of 41 °C. This low output (OVHT) is fed via the isolating diode resistor networks D19, R55
and D20, R61 to clamp the bases of switching transistors Q10 and Q12. In this way, a patient airway temperature greater
than 41 °C causes both heaters to be shut down.
A watch dog failure, which is a high output from U5g, is communicated via isolating diode D11 and resistor R31 to the
inverting input of U10c. This also ensures that both heater control circuits are clamped off in the event of a processor
crash.
inverting input of U10c. This also ensures that both heater control circuits are clamped off in the event of a processor
crash.
4.2.8
H
EATERPLATE
O
VERTEMPERATURE
Thermistor HP senses the heaterplate temperature. Should the heaterplate exceed the maximum heaterplate limit (default
110 °C) during normal operation, power to the heaterplate is discontinued until it cools below this limiting temperature.
Under certain operating conditions, for increased safety, lower maximum heaterplate temperatures can be selected. (See
Appendix A3: Programming Control Options.) Also mounted on the heaterplate is a mechanical 118 °C cut out which will
give protection should the electronic control system fail. This mechanical cut out is connected in series with the power
transformer primary and thus causes complete shut down of the humidifier should a serious fault develop. See § 3.5.1.
110 °C) during normal operation, power to the heaterplate is discontinued until it cools below this limiting temperature.
Under certain operating conditions, for increased safety, lower maximum heaterplate temperatures can be selected. (See
Appendix A3: Programming Control Options.) Also mounted on the heaterplate is a mechanical 118 °C cut out which will
give protection should the electronic control system fail. This mechanical cut out is connected in series with the power
transformer primary and thus causes complete shut down of the humidifier should a serious fault develop. See § 3.5.1.
4.2.9
W
ATCH
D
OG
During operation the processor is continually monitored for correct function. This is done by changing the state of
output port PB7 of U4 every 16.6 or 20 ms (power line frequency interrupt). This square wave, buffered by U5b, is fed to
the charge pump circuitry C16, D4, D5 and C15 which ensures that pin 13 of U5g is held hard up. Should this square
wave be interrupted for any reason, C15 will discharge through R3 giving a high output from pin 12, which drives the
trap interrupt input of U3. This high trap input forces re-initialisation of the processor which may or may not be
successful depending on the nature of the fault. The purpose of this is to ensure that if the processor should fail, and is
unable to re-initialise, it fails in a safe mode. The watch dog circuit is tested every time the humidifier is turned on by
deliberately halting program execution and waiting for initialisation via the watch dog. To indicate that the processor has
failed the high output of U5g also turns on Q3 which lights the ‘see manual’ LED10 and also turns off the display I.C. U7
to blank the digital display.
output port PB7 of U4 every 16.6 or 20 ms (power line frequency interrupt). This square wave, buffered by U5b, is fed to
the charge pump circuitry C16, D4, D5 and C15 which ensures that pin 13 of U5g is held hard up. Should this square
wave be interrupted for any reason, C15 will discharge through R3 giving a high output from pin 12, which drives the
trap interrupt input of U3. This high trap input forces re-initialisation of the processor which may or may not be
successful depending on the nature of the fault. The purpose of this is to ensure that if the processor should fail, and is
unable to re-initialise, it fails in a safe mode. The watch dog circuit is tested every time the humidifier is turned on by
deliberately halting program execution and waiting for initialisation via the watch dog. To indicate that the processor has
failed the high output of U5g also turns on Q3 which lights the ‘see manual’ LED10 and also turns off the display I.C. U7
to blank the digital display.