Cypress CY7C67300 Manual De Usuario
CY7C67300
Document #: 38-08015 Rev. *J
Page 32 of 99
Sequence Status
(Bit 3)
The Sequence Status bit indicates the state of the last received
data toggle from the device. Firmware is responsible for
monitoring and handling the sequence status. The Sequence bit
is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to
‘0’ when an error is detected in the transaction and the Error bit
is set.
data toggle from the device. Firmware is responsible for
monitoring and handling the sequence status. The Sequence bit
is only valid if the ACK bit is set to ‘1’. The Sequence bit is set to
‘0’ when an error is detected in the transaction and the Error bit
is set.
1:
DATA1
0:
DATA0
Timeout Flag
(Bit 2)
The Timeout Flag bit indicates if a timeout condition occurred for
the last transaction. A timeout condition can occur when a device
either takes too long to respond to a USB host request or takes
too long to respond with a handshake.
the last transaction. A timeout condition can occur when a device
either takes too long to respond to a USB host request or takes
too long to respond with a handshake.
1:
Timeout occurred
0:
Timeout did not occur
Error Flag
(Bit 1)
The Error Flag bit indicates a transaction failed for any reason
other than the following: timeout, receiving a NAK, or receiving
other than the following: timeout, receiving a NAK, or receiving
a STALL. Overflow and Underflow are not considered errors and
do not affect this bit. CRC5 and CRC16 errors result in an Error
flag along with receiving incorrect packet types.
do not affect this bit. CRC5 and CRC16 errors result in an Error
flag along with receiving incorrect packet types.
1:
Error detected
0:
No error detected
ACK Flag
(Bit 0)
The ACK Flag bit indicates two different conditions depending on
the transfer type. For non-isochronous transfers, this bit repre-
sents a transaction ending by receiving or sending an ACK
packet. For isochronous transfers, this bit represents a
successful transaction that is not represented by an ACK packet.
the transfer type. For non-isochronous transfers, this bit repre-
sents a transaction ending by receiving or sending an ACK
packet. For isochronous transfers, this bit represents a
successful transaction that is not represented by an ACK packet.
1:
For non-isochronous transfers, the transaction was ACKed.
For isochronous transfers, the transaction was completed
successfully
successfully
0:
For non-isochronous transfers, the transaction was not
ACKed. For isochronous transfers, the transaction did not
complete successfully
complete successfully
Host n PID Register [W]
■
Host 1 PID Register 0xC086
■
Host 2 PID Register 0xC0A6
Table 53. Host n PID Register
Bit #
15
14
13
12
11
10
9
8
Field
Reserved
Read/Write
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
PID Select
Endpoint Select
Read/Write
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0