Cypress CY7C67300 Manual De Usuario

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CY7C67300
Document #: 38-08015 Rev. *J
Page 33 of 99
Register Description
The Host n PID register is a write only register that provides the
PID and Endpoint information to the USB SIE to be used in the
next transaction. 
PID Select
 (Bits [7:4])
The PID Select field is defined in 
. ACK and NAK tokens
are automatically sent based on settings in the Host n Control
register and do not need to be written in this register.
Endpoint Select
 (Bits [3:0])
The Endpoint field allows addressing of up to 16 different
endpoints.
Reserved
Write all reserved bits with ’0’.
Host n Count Result Register [R]
Host 1 Count Result Register 0xC088
Host 2 Count Result Register 0xC0A8 
Register Description
The Host n Count Result register is a read only register that
contains the size difference in bytes between the Host Count
Value specified in the Host n Count register and the last packet
received. If an overflow or underflow condition occurs, that is the
received packet length differs from the value specified in the Host
n Count register, the Length Exception Flag bit in the Host n
Endpoint Status register is set. The value in this register is only
value when the Length Exception Flag bit is set and the Error
Flag bit is not set, both bits are in the Host n Endpoint Status
register.
Result
 (Bits [15:0])
The Result field contains the differences in bytes between the
received packet and the value specified in the Host n Count
register. If an overflow condition occurs, Result [15:10] is set to
‘111111’, a 2’s complement value indicating the additional byte
count of the received packet. If an underflow condition occurs,
Result [15:0] indicates the excess bytes count (number of bytes
not used).
Reserved
Write all reserved bits with ’0’.
Table 54.  PID Select Definition 
PID TYPE
PID Select [7:4]
SETUP
1101 (D Hex)
IN
1001 (9 Hex)
OUT
0001 (1 Hex)
SOF
0101 (5 Hex)
PREAMBLE
1100 (C Hex)
NAK
1010 (A Hex)
STALL
1110 (E Hex)
DATA0
0011 (3 Hex)
DATA1
1011 (B Hex)
Table 55.  Host n Count Result Register
Bit #
15
14
13
12
11
10
9
8
Field
Result...
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Bit #
7
6
5
4
3
2
1
0
Field
...Result
Read/Write
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0