Motorola DSP56012 Manual De Usuario
4-32
DSP56012 User’s Manual
MOTOROLA
Parallel Host Interface
Host Interface (HI)
4.4.5.6.7
ISR DMA Status (DMA)—Bit 6
The DMA status (DMA) bit indicates that the host processor has enabled the DMA
mode of the HI (HM1 or HM0 = 1). When the DMA status bit is clear, it indicates that
the DMA mode is disabled (HM0 = HM1 = 0) and no DMA operations are pending.
When DMA is set, it indicates that the DMA mode is enabled and the host processor
should not use the active DMA channel (RXH, RXM, RXL or TXH, TXM, TXL,
depending on DMA direction) to avoid conflicts with the DMA data transfers. The
channel not in use can be used for polled operation by the host and operates in the
Interrupt mode for internal DSP interrupts or polling.
mode of the HI (HM1 or HM0 = 1). When the DMA status bit is clear, it indicates that
the DMA mode is disabled (HM0 = HM1 = 0) and no DMA operations are pending.
When DMA is set, it indicates that the DMA mode is enabled and the host processor
should not use the active DMA channel (RXH, RXM, RXL or TXH, TXM, TXL,
depending on DMA direction) to avoid conflicts with the DMA data transfers. The
channel not in use can be used for polled operation by the host and operates in the
Interrupt mode for internal DSP interrupts or polling.
Note:
Hardware reset, software reset, individual reset, and Stop mode clear the
DMA status bit.
DMA status bit.
4.4.5.6.8
ISR Host Request (HOREQ)—Bit 7
The Host Request (HOREQ) bit indicates the state of the external Host Request
output pin (HOREQ). When the HOREQ status bit is cleared, it indicates that the
external HOREQ pin is deasserted and no host processor interrupts or DMA
transfers are being requested. When the HOREQ status bit is set, it indicates that the
external HOREQ pin is asserted, indicating that the DSP is interrupting the host
processor or that a DMA transfer request is occurring. The HOREQ interrupt request
can originate from either or both of two sources—the receive byte registers are full or
the transmit byte registers are empty. These conditions are indicated by the ISR
RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by
the associated request enable bit in the ICR, HOREQ will be set if one or more of the
two enabled interrupt sources is set.
output pin (HOREQ). When the HOREQ status bit is cleared, it indicates that the
external HOREQ pin is deasserted and no host processor interrupts or DMA
transfers are being requested. When the HOREQ status bit is set, it indicates that the
external HOREQ pin is asserted, indicating that the DSP is interrupting the host
processor or that a DMA transfer request is occurring. The HOREQ interrupt request
can originate from either or both of two sources—the receive byte registers are full or
the transmit byte registers are empty. These conditions are indicated by the ISR
RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by
the associated request enable bit in the ICR, HOREQ will be set if one or more of the
two enabled interrupt sources is set.
Note:
Hardware reset, software reset, individual reset, and Stop mode clear
HOREQ.
HOREQ.
4.4.5.7
Interrupt Vector Register (IVR)
The Interrupt Vector Register (IVR) is an 8-bit read/write register that typically
contains the interrupt vector number used with MC68000 family processor vectored
interrupts. Only the host processor can read and write this register. The contents of
the IVR are placed on the host data bus (H0–H7) when both the HOREQ and HACK
pins are asserted and the DMA mode is disabled.
contains the interrupt vector number used with MC68000 family processor vectored
interrupts. Only the host processor can read and write this register. The contents of
the IVR are placed on the host data bus (H0–H7) when both the HOREQ and HACK
pins are asserted and the DMA mode is disabled.
Note:
Hardware reset and software reset initialize the contents of this register to $0F,
which corresponds to the uninitialized interrupt vector in the MC68000
family.
which corresponds to the uninitialized interrupt vector in the MC68000
family.
4.4.5.8
Receive Byte Registers (RXH, RXM, RXL)
The receive byte registers are viewed by the host processor as three 8-bit read-only
registers. These registers are called Receive High (RXH), Receive Middle (RXM), and
registers. These registers are called Receive High (RXH), Receive Middle (RXM), and