Motorola DSP56012 Manual De Usuario

Data transfers from the DSP to the host processor are similar to transfers from the 
host processor to the DSP. 

registers (ISR and HSR) and control registers (ICR and HCR) used by the host 
processor and DSP CPU, respectively. The DSP CPU (see 

can poll the HTDE bit in the HSR (1) to see when it can send data to the host, or it can 
use interrupts enabled by the HTIE bit in the HCR (2). If HTIE = 1 and interrupts are 
enabled, interrupt processing begins at interrupt vector P:$0032 (3). The interrupt 
routine should write data to the HOTX (4), which will clear HTDE in the HSR. From 
the host’s viewpoint, (5) reading the RXL clears RXDF in the ISR. When RXDF = 0 
and HTDE = 0 (6) the contents of the HOTX will be transferred to the receive byte 
registers (RXH:RXM:RXL). This transfer sets RXDF in the ISR (7), which the host 
processor can poll to see if data is available or, if the RREQ bit in the ICR is set, the HI 
will interrupt the host processor with HOREQ (8).