Manual De UsuarioTabla de contenidosTable of Contents3A9B9C9D9E10Figures11Tables13Preface17Introduction251.1 The Architecture251.1.1 Addressing261.1.2 Integer Data Types261.1.3 Floating-Point Data Types261.2 21264/EV68A Microprocessor Features27Internal Architecture292.1 21264/EV68A Microarchitecture292.1.1 Instruction Fetch, Issue, and Retire Unit302.1.1.1 Virtual Program Counter Logic30Figure 2–1 21264/EV68A Block Diagram312.1.1.2 Branch Predictor312.1.1.3 Instruction-Stream Translation Buffer332.1.1.4 Instruction Fetch Logic342.1.1.5 Register Rename Maps342.1.1.6 Integer Issue Queue342.1.1.7 Floating-Point Issue Queue352.1.1.8 Exception and Interrupt Logic362.1.1.9 Retire Logic362.1.2 Integer Execution Unit362.1.3 Floating-Point Execution Unit382.1.4 External Cache and System Interface Unit392.1.4.1 Victim Address File and Victim Data File392.1.4.2 I/O Write Buffer392.1.4.3 Probe Queue392.1.4.4 Duplicate Dcache Tag Array392.1.5 Onchip Caches392.1.5.1 Instruction Cache392.1.5.2 Data Cache402.1.6 Memory Reference Unit402.1.6.1 Load Queue412.1.6.2 Store Queue412.1.6.3 Miss Address File412.1.6.4 Dstream Translation Buffer412.1.7 SROM Interface412.2 Pipeline Organization41Figure 2–8 Pipeline Organization422.2.1 Pipeline Aborts442.3 Instruction Issue Rules442.3.1 Instruction Group Definitions452.3.2 Ebox Slotting462.3.3 Instruction Latencies482.4 Instruction Retire Rules492.4.1 Floating-Point Divide/Square Root Early Retire502.5 Retire of Operate Instructions into R31/F31502.6 Load Instructions to R31 and F31512.6.1 Normal Prefetch: LDBU, LDF, LDG, LDL, LDT, LDWU, HW_LDL Instructions512.6.2 Prefetch with Modify Intent: LDS Instruction512.6.3 Prefetch, Evict Next: LDQ and HW_LDQ Instructions522.7 Special Cases of Alpha Instruction Execution522.7.1 Load Hit Speculation522.7.2 Floating-Point Store Instructions542.7.3 CMOV Instruction542.8 Memory and I/O Address Space Instructions552.8.1 Memory Address Space Load Instructions552.8.2 I/O Address Space Load Instructions552.8.3 Memory Address Space Store Instructions562.8.4 I/O Address Space Store Instructions572.9 MAF Memory Address Space Merging Rules582.10 Instruction Ordering582.11 Replay Traps592.11.1 Mbox Order Traps592.11.1.1 Load-Load Order Trap592.11.1.2 Store-Load Order Trap592.11.2 Other Mbox Replay Traps602.12 I/O Write Buffer and the WMB Instruction602.12.1 Memory Barrier (MB/WMB/TB Fill Flow)602.12.1.1 MB Instruction Processing612.12.1.2 WMB Instruction Processing612.12.1.3 TB Fill Flow622.13 Performance Measurement Support—Performance Counters632.14 Floating-Point Control Register63Figure 2–11 Floating-Point Control Register642.15 AMASK and IMPLVER Instruction Values652.15.1 AMASK662.15.2 IMPLVER662.16 Design Examples66Hardware Interface693.1 21264/EV68A Microprocessor Logic Symbol69Figure 3–1 21264/EV68A Microprocessor Logic Symbol703.2 21264/EV68A Signal Names and Functions713.3 Pin Assignments763.4 Mechanical Specifications85Figure 3–2 Package Dimensions853.5 21264/EV68A Packaging86Figure 3–3 21264/EV68A Top View (Pin Down)86Figure 3–4 21264/EV68A Bottom View (Pin Up)87Cache and External Interfaces894.1 Introduction to the External Interfaces89Figure 4–1 21264/EV68A System and Bcache Interfaces914.1.1 System Interface914.1.1.1 Commands and Addresses924.1.2 Second-Level Cache (Bcache) Interface924.2 Physical Address Considerations924.3 Bcache Structure954.3.1 Bcache Interface Signals954.3.2 System Duplicate Tag Stores954.4 Victim Data Buffer964.5 Cache Coherency964.5.1 Cache Coherency Basics964.5.2 Cache Block States974.5.3 Cache Block State Transitions984.5.4 Using SysDc Commands994.5.5 Dcache States and Duplicate Tags1014.6 Lock Mechanism1024.6.1 In-Order Processing of LDx_L/STx_C Instructions1034.6.2 Internal Eviction of LDx_L Blocks1034.6.3 Liveness and Fairness1034.6.4 Managing Speculative Store Issues with Multiprocessor Systems1044.7 System Port1044.7.1 System Port Pins1054.7.2 Programming the System Interface Clocks1064.7.3 21264/EV68A-to-System Commands1074.7.3.1 Bank Interleave on Cache Block Boundary Mode1074.7.3.2 Page Hit Mode1084.7.4 21264/EV68A-to-System Commands Descriptions1094.7.5 ProbeResponse Commands (Command[4:0] = 00001)1124.7.6 SysAck and 21264/EV68A-to-System Commands Flow Control1134.7.7 System-to-21264/EV68A Commands1144.7.7.1 Probe Commands (Four Cycles)1144.7.7.2 Data Transfer Commands (Two Cycles)1164.7.8 Data Movement In and Out of the 21264/EV68A1184.7.8.1 21264/EV68A Clock Basics1184.7.8.2 Fast Data Mode119Figure 4–5 Fast Transfer Timing Example1204.7.8.3 Fast Data Disable Mode1214.7.8.4 SysDataInValid_L and SysDataOutValid_L1224.7.8.5 SysFillValid_L1234.7.8.6 Data Wrapping1244.7.9 Nonexistent Memory Processing1264.7.10 Ordering of System Port Transactions1284.7.10.1 21264/EV68A Commands and System Probes1284.7.10.2 System Probes and SysDc Commands1304.8 Bcache Port1304.8.1 Bcache Port Pins1314.8.2 Bcache Clocking1324.8.2.1 Setting the Period of the Cache Clock1334.8.3 Bcache Transactions1354.8.3.1 Bcache Data Read and Tag Read Transactions1354.8.3.2 Bcache Data Write Transactions1364.8.3.3 Bubbles on the Bcache Data Bus1374.8.4 Pin Descriptions1384.8.4.1 BcAdd_H[23:4]1394.8.4.2 Bcache Control Pins1394.8.4.3 BcDataInClk_H and BcTagInClk_H1414.8.5 Bcache Banking1414.8.6 Disabling the Bcache for Debugging1414.9 Interrupts142Internal Processor Registers1435.1 Ebox IPRs1455.1.1 Cycle Counter Register – CC145Figure 5–1 Cycle Counter Register1455.1.2 Cycle Counter Control Register – CC_CTL145Figure 5–2 Cycle Counter Control Register1455.1.3 Virtual Address Register – VA146Figure 5–3 Virtual Address Register1465.1.4 Virtual Address Control Register – VA_CTL146Figure 5–4 Virtual Address Control Register1465.1.5 Virtual Address Format Register – VA_FORM147Figure 5–5 Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 0)147Figure 5–6 Virtual Address Format Register (VA_48 = 1, VA_FORM_32 = 0)148Figure 5–7 Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 1)1485.2 Ibox IPRs1485.2.1 ITB Tag Array Write Register – ITB_TAG148Figure 5–8 ITB Tag Array Write Register1485.2.2 ITB PTE Array Write Register – ITB_PTE148Figure 5–9 ITB PTE Array Write Register1495.2.3 ITB Invalidate All Process (ASM=0) Register – ITB_IAP1495.2.4 ITB Invalidate All Register – ITB_IA1495.2.5 ITB Invalidate Single Register – ITB_IS149Figure 5–10 ITB Invalidate Single Register1495.2.6 ProfileMe PC Register – PMPC150Figure 5–11 ProfileMe PC Register1505.2.7 Exception Address Register – EXC_ADDR150Figure 5–12 Exception Address Register1505.2.8 Instruction Virtual Address Format Register — IVA_FORM151Figure 5–13 Instruction Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 0)151Figure 5–14 Instruction Virtual Address Format Register (VA_48 = 1, VA_FORM_32 = 0)151Figure 5–15 Instruction Virtual Address Format Register (VA_48 = 0, VA_FORM_32 = 1)1515.2.9 Interrupt Enable and Current Processor Mode Register – IER_CM151Figure 5–16 Interrupt Enable and Current Processor Mode Register1525.2.10 Software Interrupt Request Register – SIRR152Figure 5–17 Software Interrupt Request Register1535.2.11 Interrupt Summary Register – ISUM153Figure 5–18 Interrupt Summary Register1535.2.12 Hardware Interrupt Clear Register – HW_INT_CLR154Figure 5–19 Hardware Interrupt Clear Register1545.2.13 Exception Summary Register – EXC_SUM155Figure 5–20 Exception Summary Register1565.2.14 PAL Base Register – PAL_BASE157Figure 5–21 PAL Base Register1575.2.15 Ibox Control Register – I_CTL157Figure 5–22 Ibox Control Register1585.2.16 Ibox Status Register – I_STAT160Figure 5–23 Ibox Status Register1615.2.17 Icache Flush Register – IC_FLUSH1635.2.18 Icache Flush ASM Register – IC_FLUSH_ASM1635.2.19 Clear Virtual-to-Physical Map Register – CLR_MAP1635.2.20 Sleep Mode Register – SLEEP1635.2.21 Process Context Register – PCTX163Figure 5–24 Process Context Register1645.2.22 Performance Counter Control Register – PCTR_CTL165Figure 5–25 Performance Counter Control Register1655.3 Mbox IPRs1675.3.1 DTB Tag Array Write Registers 0 and 1 – DTB_TAG0, DTB_TAG1167Figure 5–26 DTB Tag Array Write Registers 0 and 11675.3.2 DTB PTE Array Write Registers 0 and 1 – DTB_PTE0, DTB_PTE1168Figure 5–27 DTB PTE Array Write Registers 0 and 11685.3.3 DTB Alternate Processor Mode Register – DTB_ALTMODE168Figure 5–28 DTB Alternate Processor Mode Register1685.3.4 Dstream TB Invalidate All Process (ASM=0) Register – DTB_IAP1695.3.5 Dstream TB Invalidate All Register – DTB_IA1695.3.6 Dstream TB Invalidate Single Registers 0 and 1 – DTB_IS0,1169Figure 5–29 Dstream Translation Buffer Invalidate Single Registers1695.3.7 Dstream TB Address Space Number Registers 0 and 1 – DTB_ASN0,1170Figure 5–30 Dstream Translation Buffer Address Space Number Registers 0 and 11705.3.8 Memory Management Status Register – MM_STAT170Figure 5–31 Memory Management Status Register1705.3.9 Mbox Control Register – M_CTL171Figure 5–32 Mbox Control Register1715.3.10 Dcache Control Register – DC_CTL172Figure 5–33 Dcache Control Register1735.3.11 Dcache Status Register – DC_STAT173Figure 5–34 Dcache Status Register1745.4 Cbox CSRs and IPRs1745.4.1 Cbox Data Register – C_DATA175Figure 5–35 Cbox Data Register1755.4.2 Cbox Shift Register – C_SHFT175Figure 5–36 Cbox Shift Register1755.4.3 Cbox WRITE_ONCE Chain Description1755.4.4 Cbox WRITE_MANY Chain Description180Figure 5–37 WRITE_MANY Chain Write Transaction Example1815.4.5 Cbox Read Register (IPR) Description183Privileged Architecture Library Code1856.1 PALcode Description1856.2 PALmode Environment1866.3 Required PALcode Function Codes1876.4 Opcodes Reserved for PALcode1876.4.1 HW_LD Instruction187Figure 6–1 HW_LD Instruction Format1886.4.2 HW_ST Instruction188Figure 6–2 HW_ST Instruction Format1886.4.3 HW_RET Instruction189Figure 6–3 HW_RET Instruction Format1906.4.4 HW_MFPR and HW_MTPR Instructions1906.5 Internal Processor Register Access Mechanisms1916.5.1 IPR Scoreboard Bits1926.5.2 Hardware Structure of Explicitly Written IPRs1926.5.3 Hardware Structure of Implicitly Written IPRs1936.5.4 IPR Access Ordering1936.5.5 Correct Ordering of Explicit Writers Followed by Implicit Readers1946.5.6 Correct Ordering of Explicit Readers Followed by Implicit Writers1956.6 PALshadow Registers1956.7 PALcode Emulation of the FPCR1956.7.1 Status Flags1966.7.2 MF_FPCR1966.7.3 MT_FPCR1966.8 PALcode Entry Points1966.8.1 CALL_PAL Entry Points1966.8.2 PALcode Exception Entry Points1976.9 Translation Buffer (TB) Fill Flows1986.9.1 DTB Fill198Figure 6–5 Single-Miss DTB Instructions Flow Example1986.9.2 ITB Fill200Figure 6–6 ITB Miss Instructions Flow Example2006.10 Performance Counter Support2016.10.1 General Precautions2026.10.2 Aggregate Mode Programming Guidelines2026.10.2.1 Aggregate Mode Precautions2026.10.2.2 Operation2036.10.2.3 Aggregate Counting Mode Description2046.10.2.3.1 Cycle counting2046.10.2.3.2 Retired instructions cycles2046.10.2.3.3 Bcache miss or long latency probes cycles2046.10.2.3.4 Mbox replay traps cycles2046.10.2.4 Counter Modes for Aggregate Mode2046.10.3 ProfileMe Mode Programming Guidelines2046.10.3.1 ProfileMe Mode Precautions2046.10.3.2 Operation2056.10.3.3 ProfileMe Counting Mode Description2076.10.3.3.1 Cycle counting2076.10.3.3.2 Inum retire delay cycles2076.10.3.3.3 Retired instructions cycles2076.10.3.3.4 Bcache miss or long latency probes cycles2076.10.3.3.5 Mbox replay traps cycles2076.10.3.4 Counter Modes for ProfileMe Mode208Initialization and Configuration2097.1 Power-Up Reset Flow and the Reset_L and DCOK_H Pins209Figure 7–1 Power-Up Timing Sequence2117.1.1 Power Sequencing and Reset State for Signal Pins2117.1.2 Clock Forwarding and System Clock Ratio Configuration2127.1.3 PLL Ramp Up2147.1.4 BiST and SROM Load and the TestStat_H Pin2147.1.5 Clock Forward Reset and System Interface Initialization2157.2 Fault Reset Flow216Figure 7–2 Fault Reset Sequence of Operation2177.3 Energy Star Certification and Sleep Mode Flow217Figure 7–3 Sleep Mode Sequence of Operation2197.4 Warm Reset Flow2197.5 Array Initialization2207.6 Initialization Mode Processing220Figure 7–4 Example for Initializing Bcache2217.7 External Interface Initialization2227.8 Internal Processor Register Power-Up Reset State2227.9 IEEE 1149.1 Test Port Reset2247.10 Reset State Machine224Figure 7–5 21264/EV68A Reset State Machine State Diagram2257.11 Phase-Lock Loop (PLL) Functional Description2277.11.1 Differential Reference Clocks2277.11.2 PLL Output Clocks2277.11.2.1 GCLK2277.11.2.2 Differential 21264/EV68A Clocks2277.11.2.3 Nominal Operating Frequency2277.11.2.4 Power-Up/Reset Clocking228Error Detection and Error Handling2298.1 Data Error Correction Code2308.2 Icache Data or Tag Parity Error2308.3 Dcache Tag Parity Error2308.4 Dcache Data Single-Bit Correctable ECC Error2318.4.1 Load Instruction2318.4.2 Store Instruction (Quadword or Smaller)2328.4.3 Dcache Victim Extracts2328.5 Dcache Store Second Error2328.6 Dcache Duplicate Tag Parity Error2328.7 Bcache Tag Parity Error2338.8 Controlling Bcache Block Parity Calculation2338.9 Bcache Data Single-Bit Correctable ECC Error2338.9.1 Icache Fill from Bcache2338.9.2 Dcache Fill from Bcache2348.9.3 Bcache Victim Read2358.9.3.1 Bcache Victim Read During a Dcache/Bcache Miss2358.9.3.2 Bcache Victim Read During an ECB Instruction2358.10 Memory/System Port Single-Bit Data Correctable ECC Error2358.10.1 Icache Fill from Memory2358.10.2 Dcache Fill from Memory2368.11 Bcache Data Single-Bit Correctable ECC Error on a Probe2378.12 Double-Bit Fill Errors2378.13 Error Case Summary238Electrical Data2419.1 Electrical Characteristics2419.2 DC Characteristics2429.3 Power Supply Sequencing and Avoiding Potential Failure Mechanisms2459.4 AC Characteristics246Thermal Management25110.1 Operating Temperature25110.2 Heat Sink Specifications253Figure 10–3 Type 3 Heat Sink25510.3 Thermal Design Considerations256Testability and Diagnostics25711.1 Test Pins25711.2 SROM/Serial Diagnostic Terminal Port25811.2.1 SROM Load Operation25811.2.2 Serial Terminal Port25811.3 IEEE 1149.1 Port25911.4 TestStat_H Pin260Figure 11–1 TestStat_H Pin Timing During Power-Up Built-In Self-Test (BiST)261Figure 11–2 TestStat_H Pin Timing During Built-In Self-Initialization (BiSI)26111.5 Power-Up Self-Test and Initialization26111.5.1 Built-in Self-Test26111.5.2 SROM Initialization261Figure 11–3 SROM Content Map26211.5.2.1 Serial Instruction Cache Load Operation26211.6 Notes on IEEE 1149.1 Operation and Compliance263Alpha Instruction Set265A.1 Alpha Instruction Summary265A.2 Reserved Opcodes272A.2.1 Opcodes Reserved for Compaq272A.2.2 Opcodes Reserved for PALcode273A.3 IEEE Floating-Point Instructions273A.4 VAX Floating-Point Instructions275A.5 Independent Floating-Point Instructions275A.6 Opcode Summary276A.7 Required PALcode Function Codes277A.8 IEEE Floating-Point Conformance27821264/EV68A Boundary-Scan Register283B.1 Boundary-Scan Register283B.1.1 BSDL Description of the Alpha 21264/EV68A Boundary-Scan Register283Serial Icache Load Predecode Values295PALcode Restrictions and Guidelines297D.1 Restriction 1 : Reset Sequence Required by Retire Logic and Mapper297D.2 Restriction 2 : No Multiple Writers to IPRs in Same Scoreboard Group304D.3 Restriction 4 : No Writers and Readers to IPRs in Same Scoreboard Group304D.4 Guideline 6 : Avoid Consecutive Read-Modify-Write-Read- Modify-Write305D.5 Restriction 7 : Replay Trap, Interrupt Code Sequence, and STF/ ITOF305D.6 Restriction 9 : PALmode Istream Address Ranges306D.7 Restriction 10: Duplicate IPR Mode Bits306D.8 Restriction 11: Ibox IPR Update Synchronization307D.9 Restriction 12: MFPR of Implicitly-Written IPRs EXC_ADDR, IVA_FORM, and EXC_SUM307D.10 Restriction 13 : DTB Fill Flow Collision307D.11 Restriction 14 : HW_RET307D.12 Guideline 16 : JSR-BAD VA308D.13 Restriction 17: MTPR to DTB_TAG0/DTB_PTE0/DTB_TAG1/ DTB_PTE1308D.14 Restriction 18: No FP Operates, FP Conditional Branches, FTOI, or STF in Same Fetch Block a...308D.15 Restriction 19: HW_RET/STALL After Updating the FPCR by way of MT_FPCR in PALmode308D.16 Guideline 20 : I_CTL[SBE] Stream Buffer Enable308D.17 Restriction 21: HW_RET/STALL After HW_MTPR ASN0/ASN1308D.18 Restriction 22: HW_RET/STALL After HW_MTPR IS0/IS1309D.19 Restriction 23: HW_ST/P/CONDITIONAL Does Not Clear the Lock Flag309D.20 Restriction 24: HW_RET/STALL After HW_MTPR IC_FLUSH, IC_FLUSH_ASM, CLEAR_MAP310D.21 Restriction 25: HW_MTPR ITB_IA After Reset310D.22 Guideline 26: Conditional Branches in PALcode310D.23 Restriction 27: Reset of ‘Force-Fail Lock Flag’ State in PALcode311D.24 Restriction 28: Enforce Ordering Between IPRs Implicitly Written by Loads and Subsequent Loads311D.25 Guideline 29 : JSR, JMP, RET, and JSR_COR in PALcode311D.26 Restriction 30 : HW_MTPR and HW_MFPR to the Cbox CSR311D.27 Restriction 31 : I_CTL[VA_48] Update313D.28 Restriction 32 : PCTR_CTL Update313D.29 Restriction 33 : HW_LD Physical/Lock Use314D.30 Restriction 34 : Writing Multiple ITB Entries in the Same PALcode Flow314D.31 Guideline 35 : HW_INT_CLR Update314D.32 Restriction 36 : Updating I_CTL[SDE]314D.33 Restriction 37 : Updating VA_CTL[VA_48]314D.34 Restriction 38 : Updating PCTR_CTL314D.35 Guideline 39: Writing Multiple DTB Entries in the Same PAL Flow315D.36 Restriction 40: Scrubbing a Single-Bit Error315D.37 Restriction 41: MTPR ITB_TAG, MTPR ITB_PTE Must be in the Same Fetch Block317D.38 Restriction 42: Updating VA_CTL, CC_CTL, or CC IPRs317D.39 Restriction 43: No Trappable Instructions Along with HW_MTPR317D.40 Restriction 44: Not Applicable to the 21264/EV68A317D.41 Restriction 45: No HW_JMP or JMP Intructions in PALcode317D.42 Restriction 46: Avoiding Livelocks in Speculative Load CRD Handlers318D.43 Restriction 47: Cache Eviction for Single-Bit Cache Errors318D.44 Restriction 48: MB Bracketing of Dcache Writes to Force Bad Data ECC and Force Bad Tag Parity32021264/EV68A-to-Bcache Pin Interface321E.1 Forwarding Clock Pin Groupings321E.2 Late-Write Non-Bursting SSRAMs322E.3 Dual-Data Rate SSRAMs323Glossary327Index345Numerics345A345B345C346D347E348F349G349H349I349J351L351M351N352O352P352R353S354T355U356V356W356X356Tamaño: 4 MBPáginas: 356Language: EnglishManuales abiertas