Hoja De Datos (BX80530F1000256)Tabla de contenidosTitle Page1Contents3Revision History91.0 Introduction111.1 Terminology111.1.1 Package Terminology121.1.2 Processor Naming Convention13Table 1. Processor Identification131.2 References142.0 Electrical Specifications152.1 System Bus and Vref152.2 Clock Control and Low Power States152.2.1 Normal State—State 1162.2.2 AutoHALT Power Down State—State 216Figure 1. Clock Control State Machine162.2.3 Stop-Grant State—State 3172.2.4 HALT/Grant Snoop State—State 4172.2.5 Sleep State—State 5172.2.6 Deep Sleep State—State 6182.2.7 Clock Control182.3 Power and Ground Pins182.3.1 Phase Lock Loop (PLL) Power192.4 Processor Decoupling192.4.1 System Bus AGTL+ Decoupling192.5 Voltage Identification20Table 2. Voltage Identification Definition202.6 System Bus Unused Pins212.7 Processor System Bus Signal Groups21Table 3. Intel® Celeron® Processor System Bus Signal Groups222.7.1 Asynchronous Vs. Synchronous for System Bus Signals232.7.2 System Bus Frequency Select Signal (BSEL[1:0])232.8 Test Access Port (TAP) Connection232.9 Maximum Ratings23Table 4. Absolute Maximum Ratings242.10 Processor DC Specifications24Table 5. Voltage and Current Specifications (Sheet 1 of 5)25Table 6. AGTL+ Signal Groups DC Specifications31Table 7. Non-AGTL+ Signal Group DC Specifications322.11 AGTL+ System Bus Specifications33Table 8. Processor AGTL+ Bus Specifications332.12 System Bus AC Specifications34Table 9. System Bus AC Specifications (Clock) at the Processor Edge Fingers (for S.E.P. Package)35Table 10. System Bus AC Specifications (Clock) at the Processor Core Pins (for Both S.E.P. and PG...36Table 11. System Bus AC Specifications (SET Clock)1, 237Table 12. Valid Intel® Celeron® Processor System Bus, Core Frequency 38Table 13. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge Fingers (for S....39Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for S.E.P...39Table 15. Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins ...40Table 16. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins (for FC-PG...40Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers (for S.E...41Table 18. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins (for Both S...41Table 19. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 442Table 20. System Bus AC Specifications (Reset Conditions) (for Both S.E.P. and PPGA Packages)42Table 21. System Bus AC Specifications (Reset Conditions) (for the FC-PGA/FC-PGA2 Packages)42Table 22. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge Fingers (f...43Table 23. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core Pins (For ...44Table 24. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 345Table 25. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers (For S.E.P....45Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins (for Both S.E....46Table 27. System Bus AC Specifications (TAP Connection)1, 2, 347Figure 2. BCLK to Core Logic Offset48Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform49Figure 4. System Bus Valid Delay Timings49Figure 5. System Bus Setup and Hold Timings49Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages)50Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package)50Figure 8. Power-On Reset and Configuration Timings51Figure 9. Test Timings (TAP Connection)51Figure 10. Test Reset Timings513.0 System Bus Signal Simulations523.1 System Bus Clock (BCLK) Signal Quality Specifications and Measurement Guidelines52Table 28. BCLK Signal Quality Specifications for Simulation at the Processor Core (for Both S.E.P...52Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins (for the...53Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins53Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement (for the S.E.P. Package)54Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers543.2 AGTL+ Signal Quality Specifications and Measurement Guidelines55Table 31. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core (For Both t...55Table 32. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins (For FC-PGA...55Table 33. AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger Measurement on the S....56Figure 13. Low to High AGTL+ Receiver Ringback Tolerance563.3 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines57Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback573.3.1 Overshoot/Undershoot Guidelines573.3.2 Ringback Specification58Table 34. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Core (S...58Table 35. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement (S.E.P. Package)58Table 36. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor Pins (F...583.3.3 Settling Limit Guideline593.4 AGTL+ Signal Quality Specifications and Measurement Guidelines (FC-PGA/FC-PGA2 Packages)593.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages)593.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages)593.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 Packages)603.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages)603.4.5 Reading Overshoot/Undershoot Specification Tables (FC-PGA/ FC-PGA2 Packages)61Table 37. Example Platform Information613.4.6 Determining if a System meets the Overshoot/Undershoot Specifications (FC-PGA/FC-PGA2 Packa...62Table 38. 66MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-P...62Table 39. 33MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins (FC-PGA/FC-PG...63Figure 15. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform (FC-PGA/FC-PGA2 Packages)633.5 Non-AGTL+ Signal Quality Specifications and Measurement Guidelines64Figure 16. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1644.0 Thermal Specifications and Design Considerations654.1 Thermal Specifications65Table 40. Processor Power for the PPGA and FC-PGA Packages66Table 41. Intel® Celeron® Processor for the FC-PGA2 Package Thermal Design Power 167Figure 17. Processor Functional Die Layout (CPUID 0686h)(1)67Figure 18. Processor Functional Die Layout (up to CPUID 0683h)674.1.1 Thermal Diode68Table 42. Thermal Diode Parameters (S.E.P. and PPGA Packages)68Table 43. Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)68Table 44. Thermal Diode Interface685.0 Mechanical Specifications695.1 S.E.P. Package695.1.1 Materials Information69Figure 19. Processor Substrate Dimensions (S.E.P. Package)70Figure 20. Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)705.1.2 Signal Listing (S.E.P. Package)70Table 45. S.E.P. Package Signal Listing by Pin Number71Table 46. S.E.P. Package Signal Listing by Signal Name755.2 PPGA Package795.2.1 PPGA Package Materials Information79Figure 21. Package Dimensions (PPGA Package)79Table 47. Package Dimensions (PPGA Package)80Table 48. Information Summary (PPGA Package)805.2.2 PPGA Package Signal Listing81Figure 22. PPGA Package (Pin Side View)81Table 49. PPGA Package Signal Listing by Pin Number82Table 50. PPGA Package Signal Listing in Order by Signal Name875.3 FC-PGA/FC-PGA2 Packages925.3.1 FC-PGA Mechanical Specifications92Figure 23. Package Dimensions (FC-PGA Package)92Table 51. Package Dimensions (FC-PGA Package)93Table 52. Processor Die Loading Parameters (FC-PGA Package)935.3.2 Mechanical Specifications (FC-PGA2 Package)94Figure 24. Package Dimensions (FC-PGA2 Package)94Table 53. Package Dimensions (FC-PGA2 Package)95Table 54. Processor Case Loading Parameters (FC-PGA2 Package)95Figure 25. Volumetric Keep-Out96Figure 26. Component Keep-Out965.3.3 FC-PGA/FC-PGA2 Package Signal List97Figure 27. Package Dimensions (FC-PGA/FC-PGA2 Packages)97Table 55. FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name98Table 56. FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number1035.4 Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages)108Figure 28. Top Side Processor Markings (PPGA Package)108Figure 29. Top Side Processor Markings (FC-PGA Package)108Figure 30. Top Side Processor Markings (FC-PGA2 Package)1085.5 Heatsink Volumetric Keepout Zone Guidelines1096.0 Boxed Processor Specifications1106.1 Mechanical Specifications for the Boxed Intel® Celeron® Processor1106.1.1 Mechanical Specifications for the S.E.P. Package110Figure 31. Retention Mechanism for the Boxed Intel® Celeron® Processor in the S.E.P. Package111Figure 32. Side View Space Requirements for the Boxed Processor in the S.E.P. Package111Figure 33. Front View Space Requirements for the Boxed Processor in the S.E.P. Package112Table 57. Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package1126.1.2 Mechanical Specifications for the PPGA Package113Figure 34. Boxed Intel® Celeron® Processor in the PPGA Package113Figure 35. Side View Space Requirements for the Boxed Processor in the PPGA Package1136.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages114Figure 36. Conceptual Drawing of the Boxed Intel® Celeron® Processor in the 370-Pin Socket (FC-PG...114Figure 37. Dimensions of Mechanical Step Feature in Heatsink Base for the FC-PGA/ FC-PGA2 Packages1146.2 Thermal Specifications1156.2.1 Thermal Requirements for the Boxed Intel® Celeron® Processor115Figure 38. Top View Airspace Requirements for the Boxed Processor in the S.E.P. Package115Figure 39. Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the FC-PGA/...116Figure 40. Volumetric Keepout Requirements for The Boxed Fan Heatsink116Figure 41. Clip Keepout Requirements for the 370-Pin (Top View)1176.3 Electrical Requirements for the Boxed Intel® Celeron® Processor1176.3.1 Electrical Requirements117Figure 42. Boxed Processor Fan Heatsink Power Cable Connector Description118Table 58. Fan Heatsink Power and Signal Specifications118Figure 43. Motherboard Power Header Placement for the S.E.P. Package119Figure 44. Motherboard Power Header Placement Relative to the 370-pin Socket1197.0 Processor Signal Description120Table 59. Alphabetical Signal Reference (Sheet 1 of 7)1207.1 Signal Summaries126Table 60. Output Signals126Table 61. Input Signals127Table 62. Input/Output Signals (Single Driver)128Table 63. Input/Output Signals (Multiple Driver)128Tamaño: 3 MBPáginas: 128Language: EnglishManuales abiertas
Manual De Usuario (YK80542KC0013M)Tabla de contenidos1 Introduction111.1 Overview111.2 Processor Abstraction Layer111.3 Mixing Processors of Different Frequencies and Cache Sizes121.4 Terminology121.5 State of Data121.6 Reference Documents132 Electrical Specifications152.1 Itanium® 2 Processor System Bus152.1.1 System Bus Power Pins152.1.2 System Bus No Connect152.2 System Bus Signals152.2.1 Signal Groups152.2.2 Signal Descriptions162.3 Package Specifications172.4 Signal Specifications182.4.1 Maximum Ratings222.5 System Bus Signal Quality Specifications and Measurement Guidelines232.5.1 Overshoot/Undershoot Magnitude232.5.2 Overshoot/Undershoot Pulse Duration242.5.3 Activity Factor242.5.4 Reading Overshoot/Undershoot Specification Tables252.5.5 Determining if a System Meets the Overshoot/Undershoot Specifications252.5.6 Wired-OR Signals282.6 Power Pod Connector Signals302.7 Itanium® 2 Processor System Bus Clock and Processor Clocking322.8 Recommended Connections for Unused Pins353 Pinout Specifications374 Mechanical Specifications694.1 Mechanical Dimensions694.2 Package Marking724.2.1 Processor Top-Side Marking724.2.2 Processor Bottom-Side Marking725 Thermal Specifications755.1 Thermal Features755.1.1 Thermal Alert755.1.2 Enhanced Thermal Management765.1.3 Thermal Trip765.2 Case Temperature766 System Management Feature Specifications796.1 System Management Bus796.1.1 System Management Bus Interface796.1.2 System Management Interface Signals796.1.3 SMBus Device Addressing816.2 Processor Information ROM826.3 Scratch EEPROM856.4 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions856.5 Thermal Sensing Device866.6 Thermal Sensing Device Supported SMBus Transactions876.7 Thermal Sensing Device Registers886.7.1 Thermal Reference Registers886.7.2 Thermal Limit Registers896.7.3 Status Register896.7.4 Configuration Register896.7.5 Conversion Rate Register90A Signals Reference91A.1 Alphabetical Signals Reference91A.1.1 A[49:3]# (I/O)91A.1.2 A20M# (I)91A.1.3 ADS# (I/O)91A.1.4 AP[1:0]# (I/O)91A.1.5 ASZ[1:0]# (I/O)91A.1.6 ATTR[3:0]# (I/O)92A.1.7 BCLKp/BCLKn (I)92A.1.8 BE[7:0]# (I/O)92A.1.9 BERR# (I/O)93A.1.10 BINIT# (I/O)94A.1.11 BNR# (I/O)94A.1.12 BPM[5:0]# (I/O)94A.1.13 BPRI# (I)94A.1.14 BR[0]# (I/O) and BR[3:1]# (I)94A.1.15 BREQ[3:0]# (I/O)95A.1.16 CCL# (I/O)96A.1.17 CPUPRES# (O)96A.1.18 D[127:0]# (I/O)96A.1.19 D/C# (I/O)96A.1.20 DBSY# (I/O)96A.1.21 DBSY_C1# (O)96A.1.22 DBSY_C2# (O)97A.1.23 DEFER# (I)97A.1.24 DEN# (I/O)97A.1.25 DEP[15:0]# (I/O)97A.1.26 DHIT# (I)97A.1.27 DPS# (I/O)98A.1.28 DRDY# (I/O)98A.1.29 DRDY_C1# (O)98A.1.30 DRDY_C2# (O)98A.1.31 DSZ[1:0]# (I/O)98A.1.32 EXF[4:0]# (I/O)98A.1.33 FCL# (I/O)99A.1.34 FERR# (O)99A.1.35 GSEQ# (I)99A.1.36 HIT# (I/O) and HITM# (I/O)99A.1.37 ID[9:0]# (I)99A.1.38 IDS# (I)99A.1.39 IGNNE# (I)100A.1.40 INIT# (I)100A.1.41 INT (I)100A.1.42 IP[1:0]# (I)100A.1.43 LEN[2:0]# (I/O)100A.1.44 LINT[1:0] (I)101A.1.45 LOCK# (I/O)101A.1.46 NMI (I)101A.1.47 OWN# (I/O)101A.1.48 PMI# (I)101A.1.49 PWRGOOD (I)101A.1.50 REQ[5:0]# (I/O)101A.1.51 RESET# (I)102A.1.52 RP# (I/O)102A.1.53 RS[2:0]# (I)103A.1.54 RSP# (I)103A.1.55 SBSY# (I/O)103A.1.56 SBSY_C1# (O)103A.1.57 SBSY_C2# (O)103A.1.58 SPLCK# (I/O)103A.1.59 STBn[7:0]# and STBp[7:0]# (I/O)104A.1.60 TCK (I)104A.1.61 TDI (I)104A.1.62 TDO (O)104A.1.63 THRMTRIP# (O)104A.1.64 THRMALERT# (O)105A.1.65 TMS (I)105A.1.66 TND# (I/O)105A.1.67 TRDY# (I)105A.1.68 TRST# (I)105A.1.69 WSNP# (I/O)105A.2 Signal Summaries105Tamaño: 3 MBPáginas: 108Language: EnglishManuales abiertas
