Manual De Usuario (BX80562QX9300)Tabla de contenidosContents3Figures4Tables41 Introduction71.1 Terminology71.2 References9Table 1. References92 Low Power Features112.1 Clock Control and Low Power States11Figure 1. Core Low Power States12Figure 2. Package Low Power States13Table 2. Coordination of Core Low Power States at the Package Level132.1.1 Core Low Power State Descriptions132.1.1.1 Core C0 State132.1.1.2 Core C1/AutoHALT Powerdown State132.1.1.3 Core C1/MWAIT Powerdown State142.1.1.4 Core C2 State142.1.1.5 Core C3 State142.1.1.6 Core C4 State142.1.2 Package Low Power State Descriptions142.1.2.1 Normal State142.1.2.2 Stop-Grant State152.1.2.3 Stop-Grant Snoop State152.1.2.4 Sleep State152.1.2.5 Deep Sleep State162.1.2.6 Deeper Sleep State162.2 Enhanced Intel SpeedStep® Technology172.3 Extended Low Power States172.4 FSB Low Power Enhancements182.4.1 Dual Intel Dynamic Acceleration192.5 Processor Power Status Indicator (PSI-2) Signal19Figure 3. PSI-2 Functionality Logic Diagram193 Electrical Specifications213.1 Power and Ground Pins213.2 Decoupling Guidelines213.2.1 VCC Decoupling213.2.2 FSB AGTL+ Decoupling213.2.3 FSB Clock (BCLK[1:0]) and Processor Clocking213.3 Voltage Identification and Power Sequencing22Table 3. Voltage Identification Definition (Sheet 1 of 4)233.4 Catastrophic Thermal Protection263.5 Reserved and Unused Pins263.6 FSB Frequency Select Signals (BSEL[2:0])27Table 4. BSEL[2:0] Encoding for BCLK Frequency273.7 FSB Signal Groups27Table 5. FSB Pin Groups283.8 CMOS Signals293.9 Maximum Ratings29Table 6. Processor Absolute Maximum Ratings293.10 Processor DC Specifications30Table 7. Voltage and Current Specifications for the Quad-Core Extreme Mobile Processors (Sheet 1 of 2)30Table 8. Voltage and Current Specifications for the Quad-Core Mobile Processors (Sheet 1 of 2)31Figure 4. Active VCC and ICC Loadline for Quad-Core Extreme Mobile Processor33Figure 5. Deeper Sleep VCC and ICC Loadline for Quad-Core Extreme Mobile Processor34Table 9. AGTL+ Signal Group DC Specifications (Sheet 1 of 2)34Table 10. CMOS Signal Group DC Specifications36Table 11. Open Drain Signal Group DC Specifications364 Package Mechanical Specifications and Pin Information374.1 Package Mechanical Specifications37Figure 6. Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 1 of 2)38Figure 7. Quad-Core Processor Micro-FCPGA Package Drawing (Sheet 2 of 2)394.2 Processor Pinout and Pin List40Figure 8. Quad-Core Processor Pinout (Top Package View, Left Side)40Figure 9. Quad-Core Processor Pinout (Top Package View, Right Side)41Table 12. Pin Listing by Pin Name42Table 13. Pin Listing by Pin Number49Table 14. Signal Description (Sheet 1 of 9)57Table 15. New Pins for the Quad-Core Mobile Processor665 Thermal Specifications and Design Considerations67Table 16. Processor Power Specifications675.1 Monitoring Die Temperature685.1.1 Thermal Diode68Table 17. Thermal Diode Interface69Table 18. Thermal Diode Parameters Using Transistor Model695.1.2 Intel® Thermal Monitor695.1.3 Digital Thermal Sensor715.2 PROCHOT# Signal Pin72Tamaño: 1 MBPáginas: 72Language: EnglishManuales abiertas